User manual TEXAS INSTRUMENTS AM1802 ARM MICROPROCESSOR FEATURES 11-2010

[. . . ] AM1802 www. ti. com SPRS710 ­ NOVEMBER 2010 AM1802 ARM Microprocessor Check for Samples: AM1802 1 AM1802 ARM Microprocessor 1. 1 12 Features NAND (8-/16-Bit-Wide Data) 16-Bit SDRAM With 128 MB Address Space ­ DDR2/Mobile DDR Memory Controller · 16-Bit DDR2 SDRAM With 512 MB Address Space or · 16-Bit mDDR SDRAM With 256 MB Address Space Three Configurable 16550 type UART Modules: ­ With Modem Control Signals ­ 16-byte FIFO ­ 16x or 13x Oversampling Option Two Serial Peripheral Interfaces (SPI) Each With Multiple Chip-Selects One Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO) Interfaces One Master/Slave Inter-Integrated Circuit (I2C BusTM) One Host-Port Interface (HPI) With 16-Bit-Wide Muxed Address/Data Bus For High Bandwidth USB 2. 0 OTG Port With Integrated PHY (USB0) ­ USB 2. 0 High-/Full-Speed Client ­ USB 2. 0 High-/Full-/Low-Speed Host ­ End Point 0 (Control) ­ End Points 1, 2, 3, 4 (Control, Bulk, Interrupt or ISOC) Rx and Tx One Multichannel Audio Serial Port: ­ Transmit/Receive Clocks ­ Two Clock Zones and 16 Serial Data Pins ­ Supports TDM, I2S, and Similar Formats ­ DIT-Capable ­ FIFO buffers for Transmit and Receive 10/100 Mb/s Ethernet MAC (EMAC): ­ IEEE 802. 3 Compliant ­ MII Media Independent Interface ­ RMII Reduced Media Independent Interface ­ Management Data I/O (MDIO) Module Real-Time Clock With 32 KHz Oscillator and Separate Power Rail Three One 64-Bit General-Purpose Timers (Each configurable as Two 32-Bit Timers) · · · Highlights ­ 300-MHz ARM926EJ-STM RISC Core ­ ARM9 Memory Architecture ­ Enhanced Direct-Memory-Access Controller 3 (EDMA3) ­ Two External Memory Interfaces ­ Three Configurable 16550 type UART Modules ­ Two Serial Peripheral Interfaces (SPI) ­ Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO) ­ One Master/Slave Inter-Integrated Circuit ­ USB 2. 0 OTG Port With Integrated PHY ­ One Multichannel Audio Serial Port ­ 10/100 Mb/s Ethernet MAC (EMAC) ­ Three 64-Bit General-Purpose Timers ­ One 64-bit General-Purpose/Watchdog Timer · 300-MHz ARM926EJ-STM RISC MPU · ARM926EJ-S Core ­ 32-Bit and 16-Bit (Thumb®) Instructions ­ Single Cycle MAC ­ ARM® Jazelle® Technology ­ EmbeddedICE-RTTM for Real-Time Debug · ARM9 Memory Architecture ­ 16K-Byte Instruction Cache ­ 16K-Byte Data Cache ­ 8K-Byte RAM (Vector Table) ­ 64K-Byte ROM · Enhanced Direct-Memory-Access Controller 3 (EDMA3): ­ 2 Channel Controllers ­ 3 Transfer Controllers ­ 64 Independent DMA Channels ­ 16 Quick DMA Channels ­ Programmable Transfer Burst Size · 128K-Byte On-chip Memory · 1. 8V or 3. 3V LVCMOS IOs (except for USB and DDR2 interfaces) · Two External Memory Interfaces: ­ EMIFA · NOR (8-/16-Bit-Wide Data) 1 · · · · · · · · · · 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. ARM926EJ-S is a trademark of ARM Limited. Copyright © 2010, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. AM1802 SPRS710 ­ NOVEMBER 2010 www. ti. com · One 64-bit General-Purpose/Watchdog Timer (Configurable as Two 32-bit General-Purpose Timers) · 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZWT Suffix], 0. 80-mm Ball Pitch · Industrial Temperature · Community Resources ­ TI E2E Community ­ TI Embedded Processors Wiki 2 AM1802 ARM Microprocessor Submit Documentation Feedback Product Folder Link(s): AM1802 Copyright © 2010, Texas Instruments Incorporated AM1802 www. ti. com SPRS710 ­ NOVEMBER 2010 1. 2 Trademarks All trademarks are the property of their respective owners. Copyright © 2010, Texas Instruments Incorporated AM1802 ARM Microprocessor Submit Documentation Feedback Product Folder Link(s): AM1802 3 AM1802 SPRS710 ­ NOVEMBER 2010 www. ti. com 1. 3 Description The device is a Low-power applications processor based on ARM926EJ-STM. [. . . ] 1 2 3 4 5 6 7 8 9 10 11 12 (1) (2) (3) (4) Parameter HS Bypass Capacitor Package Size Distance from HS bypass capacitor to device being bypassed Number of connection vias for each HS bypass capacitor Trace length from bypass capacitor contact to connection via Number of connection vias for each DDR2/mDDR device power or ground balls Trace length from DDR2/mDDR device power ball to connection via DDR_DVDD18 Supply HS Bypass Capacitor Count DDR_DVDD18 Supply HS Bypass Capacitor Total Capacitance DDR#1 HS Bypass Capacitor Count DDR#1 HS Bypass Capacitor Total Capacitance DDR#2 HS Bypass Capacitor Count DDR#2 HS Bypass Capacitor Total Capacitance 10 0. 6 8 0. 4 8 0. 4 2 1 1 35 30 Min Max 0402 250 Unit 10 Mils Mils Vias Mils Vias Mils Devices mF Devices mF Devices mF See Notes See Note (3) (4) Notes See Note See Note (1) (2) See Note See Note (3) (3) , (4) LxW, 10 mil units, i. e. , a 0402 is a 40x20 mil surface mount capacitor An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. These devices should be placed as close as possible to the device being bypassed. Only used on dual-memory systems Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1802 93 AM1802 SPRS710 ­ NOVEMBER 2010 www. ti. com 5. 11. 3. 8 Net Classes Table 5-31 lists the clock net classes for the DDR2/mDDR interface. Table 5-32 lists the signal net classes, and associated clock net classes, for the signals in the DDR2/mDDR interface. These net classes are used for the termination and routing rules that follow. Clock Net Class Definitions Clock Net Class CK DQS0 DQS1 Pin Names DDR_CLKP / DDR_CLKN DDR_DQS[0] DDR_DQS[1] Table 5-32. Signal Net Class Definitions Signal Net Class ADDR_CTRL D0 D1 DQGATE Associated Clock Net Class CK DQS0 DQS1 CK, DQS0, DQS1 Pin Names DDR_BA[2:0], DDR_A[13:0], DDR_CS, DDR_CAS, DDR_RAS, DDR_WE, DDR_CKE DDR_D[7:0], DDR_DQM0 DDR_D[15:8], DDR_DQM1 DDR_DQGATE0, DDR_DQGATE1 5. 11. 3. 9 DDR2/mDDR Signal Termination No terminations of any kind are required in order to meet signal integrity and overshoot requirements. Serial terminators are permitted, if desired, to reduce EMI risk; however, serial terminations are the only type permitted. 1 2 3 4 (1) (2) (3) (4) Parameter CK Net Class ADDR_CTRL Net Class Data Byte Net Classes (DQS[0], DQS[1], D0, D1) DQGATE Net Class (DQGATE) Min 0 0 0 0 22 22 10 Typ Max 10 Zo Zo Zo Unit See Note Notes (1) (1) (2) (3) See Notes See Notes See Notes , , , , (1) (2) (3) (4) , , , (1) (2) (3) Only series termination is permitted, parallel or SST specifically disallowed. Terminator values larger than typical only recommended to address EMI issues. When no termination is used on data lines (0 ), the DDR2/mDDR devices must be programmed to operate in 60% strength mode. 94 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1802 Copyright © 2010, Texas Instruments Incorporated AM1802 www. ti. com SPRS710 ­ NOVEMBER 2010 5. 11. 3. 10 VREF Routing VREF is used as a reference by the input buffers of the DDR2/mDDR memories as well as the device. VREF is intended to be half the DDR2/mDDR power supply voltage and should be created using a resistive divider as shown in Figure 5-16. Figure 5-20 shows the layout guidelines for VREF. VREF Bypass Capacitor DDR2/mDDR Device A1 VREF Nominal Minimum Trace Width is 20 Mils DDR2/mDDR A1 Neck down to minimum in BGA escape regions is acceptable. Narrowing to accomodate via congestion for short distances is also acceptable. Best performance is obtained if the width of VREF is maximized. Figure 5-20. VREF Routing and Topology Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1802 95 AM1802 SPRS710 ­ NOVEMBER 2010 www. ti. com 5. 11. 3. 11 DDR2/mDDR CK and ADDR_CTRL Routing Figure 5-21 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A should be maximized. A1 T A C A1 Figure 5-21. 1 2 3 4 5 6 7 8 9 10 11 Parameter Center to Center CK-CKN Spacing CK A to B/A to C Skew Length Mismatch CK B to C Skew Length Mismatch Center to center CK to other DDR2/mDDR trace spacing CK/ADDR_CTRL nominal trace length ADDR_CTRL to CK Skew Length Mismatch ADDR_CTRL to ADDR_CTRL Skew Length Mismatch Center to center ADDR_CTRL to other DDR2/mDDR trace spacing Center to center ADDR_CTRL to other ADDR_CTRL trace spacing ADDR_CTRL A to B/A to C Skew Length Mismatch ADDR_CTRL B to C Skew Length Mismatch 4w 3w (1) (1) (1) Min DDR2/mDDR Controller Typ B Max 2w (1) Unit See Note Mils Mils See Note See Note Notes (2) (3) 25 25 4w (2) (4) CACLM-50 CACLM CACLM+50 100 100 Mils Mils Mils See Note See Note See Note 100 100 Mils Mils See Note (2) (2) (3) (1) (2) (3) (4) w = PCB trace width as defined in Table 5-27. Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion. CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes. 96 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1802 Copyright © 2010, Texas Instruments Incorporated AM1802 www. ti. com SPRS710 ­ NOVEMBER 2010 Figure 5-22 shows the topology and routing for the DQS and D net class; the routes are point to point. Skew matching across bytes is not needed nor recommended. T A1 T A1 E1 Figure 5-22. [. . . ] In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. [. . . ]