User manual TEXAS INSTRUMENTS AM1810 ARM MICROPROCESSOR FEATURES FOR PROFIBUS 11-2010

[. . . ] AM1810 www. ti. com SPRS709 ­ NOVEMBER 2010 AM1810 ARM Microprocessor For PROFIBUS Check for Samples: AM1810 1 AM1810 ARM Microprocessor 1. 1 12 Features · 1. 8V or 3. 3V LVCMOS IOs (except for USB and DDR2 interfaces) · Two External Memory Interfaces: ­ EMIFA · NOR (8-/16-Bit-Wide Data) · NAND (8-/16-Bit-Wide Data) · 16-Bit SDRAM With 128 MB Address Space ­ DDR2/Mobile DDR Memory Controller · 16-Bit DDR2 SDRAM With 512 MB Address Space or · 16-Bit mDDR SDRAM With 256 MB Address Space · Three Configurable 16550 type UART Modules: ­ With Modem Control Signals ­ 16-byte FIFO ­ 16x or 13x Oversampling Option · LCD Controller · Two Serial Peripheral Interfaces (SPI) Each With Multiple Chip-Selects · Two Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO) Interfaces · Two Master/Slave Inter-Integrated Circuit (I2C BusTM) · One Host-Port Interface (HPI) With 16-Bit-Wide Muxed Address/Data Bus For High Bandwidth · Programmable Real-Time Unit Subsystem (PRUSS) With Profibus ­ Two Independent Programmable Realtime Unit (PRU) Cores · 32-Bit Load/Store RISC architecture · 4K Byte instruction RAM per core · 512 Bytes data RAM per core · PRU Subsystem (PRUSS) can be disabled via software to save power · Register 30 of each PRU is exported from the subsystem in addition to the normal R31 output of the PRU cores. ­ Standard power management mechanism · Clock gating · Entire subsystem under a single PSC clock gating domain · Highlights ­ 375-MHz ARM926EJ-STM RISC Core ­ ARM9 Memory Architecture ­ Programmable Real-Time Unit Subsystem (With Profibus) ­ Enhanced Direct-Memory-Access Controller 3 (EDMA3) ­ Two External Memory Interfaces ­ Three Configurable 16550 type UART Modules ( Including one (UART1 or UART2) designated for PROFIBUS interface. ) ­ Two Serial Peripheral Interfaces (SPI) ­ Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO) ­ Two Master/Slave Inter-Integrated Circuit ­ USB 2. 0 OTG Port With Integrated PHY ­ One Multichannel Audio Serial Port ­ 10/100 Mb/s Ethernet MAC (EMAC) ­ Three 64-Bit General-Purpose Timers ­ One 64-bit General-Purpose/Watchdog Timer ­ TwoEnhanced Pulse Width Modulators ­ Three 32-Bit Enhanced Capture Modules · 375MHz ARM926EJ-STM RISC MPU · ARM926EJ-S Core ­ 32-Bit and 16-Bit (Thumb®) Instructions ­ Single Cycle MAC ­ ARM® Jazelle® Technology ­ EmbeddedICE-RTTM for Real-Time Debug · ARM9 Memory Architecture ­ 16K-Byte Instruction Cache ­ 16K-Byte Data Cache ­ 8K-Byte RAM (Vector Table) ­ 64K-Byte ROM · Enhanced Direct-Memory-Access Controller 3 (EDMA3): ­ 2 Channel Controllers ­ 3 Transfer Controllers ­ 64 Independent DMA Channels ­ 16 Quick DMA Channels ­ Programmable Transfer Burst Size · 128K-Byte On-chip Memory 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. ARM926EJ-S is a trademark of ARM Limited. Copyright © 2010, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. [. . . ] SATA Interface High Level Schematic 5. 14. 2. 2 Compatible SATA Components and Modes Table 5-43 shows the compatible SATA components and supported modes. Note that the only supported configuration is an internal cable from the processor host to the SATA device. SATA Supported Modes PARAMETER Transfer Rates eSATA xSATA Backplane Internal Cable MIN 1. 5 MAX 3. 0 UNIT Gbps No No No Yes SUPPORTED 5. 14. 2. 3 PCB Stackup Specifications Table 5-44 shows the stackup and feature sizes required for SATA. SATA PCB Stackup Specifications PARAMETER PCB Routing/Plane Layers Signal Routing Layers Number of ground plane cuts allowed within SATA routing region Number of layers between SATA routing region and reference ground plane Copyright © 2010, Texas Instruments Incorporated MIN 4 2 TYP 6 3 MAX UNIT Layers Layers 0 0 Layers Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1810 129 AM1810 SPRS709 ­ NOVEMBER 2010 www. ti. com Table 5-44. SATA PCB Stackup Specifications (continued) PARAMETER PCB Routing Feature Size PCB Trace Width w PCB BGA escape via pad size PCB BGA escape via hole size Device BGA pad size (1) (1) MIN 4 4 TYP MAX UNIT Mils Mils 18 8 Mils Mils Please refer to the Flip Chip Ball Grid Array Package Reference Guide (SPRU811) for device BGA pad size. 5. 14. 2. 4 Routing Specifications The SATA data signal traces are edge-coupled and must be routed to achieve exactly 100 Ohms differential impedance. This is impacted by trace width, trace spacing, distance between planes, and dielectric material. Verify with a proper PCB manufacturing tool that the trace geometry for both data signal pairs results in exactly 100 ohms differential impedance traces. Table 5-45 shows the routing specifications for the data and REFCLK signals . SATA Routing Specifications PARAMETER Device to SATA header trace length REFCLK trace length from oscillator to Device Number of stubs allowed on SATA traces TX/RX pair differential impedance Number of vias on each SATA trace SATA differential pair to any other trace spacing (1) (2) Vias must be used in pairs with their distance minimized. 2*DS (2) MIN TYP MAX 7000 2000 0 UNIT Mils Mils Stubs Ohms Vias (1) 100 3 5. 14. 2. 5 Coupling Capacitors AC coupling capacitors are required on the receive data pair as well as the REFCLK pair. SATA Bypass and Coupling Capacitors Requirements PARAMETER SATA AC coupling capacitor value SATA AC coupling capacitor package size (1) (2) LxW, 10 mil units, i. e. , a 0402 is a 40x20 mil surface mount capacitor. MIN 0. 3 TYP 10 MAX 12 0603 UNIT nF 10 Mils (2) (1) 5. 14. 2. 6 SATA Interface Clock Source requirements A high-quality, low-jitter differential clock source is required for the SATA PHY. The SATA interface requires a LVDS differential clock source to be provided at signals SATA_REFCLKP and SATA_REFCLKN. The clock source should be placed physically as close to the processor as possible. SATA Input Clock Source Requirements PARAMETER Clock Frequency (1) 130 (1) MIN 75 TYP MAX 375 UNIT MHz Discrete clock frequency points are supported based on the PLL multiplier used in the SATA PHY. Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1810 Copyright © 2010, Texas Instruments Incorporated AM1810 www. ti. com SPRS709 ­ NOVEMBER 2010 Table 5-47. SATA Input Clock Source Requirements (continued) PARAMETER Jitter Duty Cycle Rise/Fall Time 40 700 MIN TYP MAX 50 60 UNIT ps pk-pk % ps 5. 14. 3 SATA Unused Signal Configuration If the SATA interface is not used, the SATA signals should be configured as shown below. Unused SATA Signal Configuration SATA Signal Name SATA_RXP SATA_RXN SATA_TXP SATA_TXN SATA_REFCLKP SATA_REFCLKN SATA_MPSWITCH SATA_CP_DET SATA_CP_POD SATA_LED SATA_REG SATA_VDDR SATA_VDD SATA_VSS No Connect No Connect No Connect No Connect No Connect No Connect May be used as GPIO or other peripheral function May be used as GPIO or other peripheral function May be used as GPIO or other peripheral function May be used as GPIO or other peripheral function No Connect No Connect Prior to silicon revision 2. 0, this supply must be connected to a static 1. 2V nominal supply. For silicon revision 2. 0 and later, this supply may be left unconnected for additional power conservation. Vss Configuration if SATA peripheral is not used Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1810 131 AM1810 SPRS709 ­ NOVEMBER 2010 www. ti. com 5. 15 Multichannel Audio Serial Port (McASP) The McASP serial port is specifically designed for multichannel audio applications. Its key features are: · Flexible clock and frame sync generation logic and on-chip dividers · Up to sixteen transmit or receive data pins and serializers · Large number of serial data format options, including: ­ TDM Frames with 2 to 32 time slots per frame (periodic) or 1 slot per frame (burst) ­ Time slots of 8, 12, 16, 20, 24, 28, and 32 bits ­ First bit delay 0, 1, or 2 clocks ­ MSB or LSB first bit order ­ Left- or right-aligned data words within time slots · DIT Mode with 384-bit Channel Status and 384-bit User Data registers · Extensive error checking and mute generation logic · All unused pins GPIO-capable · · Transmit & Receive FIFO Buffers allow the McASP to operate at a higher sample rate by making it more tolerant to DMA latency. Dynamic Adjustment of Clock Dividers ­ Clock Divider Value may be changed without resetting the McASP Pins Receive Logic C lo ck /F ra m e G e n e ra to r State Machine Clock Check and Error Detection Tra n s m it L o g ic C lo ck /F ra m e G e n e ra to r State Machine Serializer 0 Serializer 1 AHCLKRx ACLKRx AFSRx AMUTEINx AMUTEx AFSXx ACLKXx AHCLKXx AXRx[0] AXRx[1] Function Receive Master Clock Receive Bit Clock R e c e iv e L e ft/R ig h t C lo ck o r F ra m e S y n c The McASP DOES NOT have a dedicated AMUTEIN pin. [. . . ] In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. [. . . ]