User manual TEXAS INSTRUMENTS AM3517 DATA MANUAL REV B

[. . . ] AM3517, AM3505 www. ti. com SPRS550B ­ OCTOBER 2009 ­ REVISED JULY 2010 AM3517/05 ARM Microprocessor Check for Samples: AM3517, AM3505 1 AM3517/05 ARM Microprocessor 1. 1 1234 Features (McBSP2) ­ SIDETONE Core Support (McBSP2 and 3 Only) For Filter, Gain, and Mix Operations ­ 128-Channel Transmit/Receive Mode ­ Direct Interface to I2S and PCM Device and TDM Buses · HDQ/1-Wire Interface · 4 UARTs (One with Infrared Data Association [IrDA] and Consumer Infrared [CIR] Modes) · 3 Master/Slave High-Speed Inter-Integrated Circuit (I2C) Controllers · 12 32-bit General Purpose Timers · 1 32-bit Watchdog Timer · 1 32-bit 32-kHz Sync Timer · Up to 186 General-Purpose I/O (GPIO) Pins · Display subsystem ­ Parallel Digital Output ­ Up to 24-Bit RGB ­ Supports Up to 2 LCD Panels ­ Support for Remote Frame Buffer Interface (RFBI) LCD Panels ­ Two 10-bit Digital-to-Analog Converters (DACs) Supporting · Composite NTSC/PAL Video · Luma/Chroma Separate Video (S-Video) ­ Rotation 90, 180, and 270 degrees ­ Resize Images From 1/4x to 8x ­ Color Space Converter ­ 8-bit Alpha Blending · Video Processing Front End (VPFE) 16-bit Video Input Port ­ RAW Data Interface ­ 75-MHz Maximum Pixel Clock ­ Supports REC656/CCIR656 Standard ­ Supports YCbCr422 Format (8-bit or 16-bit With Discrete Horizontal and Vertical Sync Signals) ­ Generates Optical Black Clamping Signals · AM3517/05 ARM Microprocessor: ­ Software Compatible with OMAPTM 3 Processors ­ MPU Subsystem · 600-MHz ARM CortexTM-A8 Core · NEONTM SIMD Coprocessor and Vector floating point (FP) co-processor ­ Memory Interfaces: · 16/32- bit mDDR/DDR2 Interface with 1 GByte total addressable space · General Purpose Memory Interface supporting 16-bit Wide Multiplexed Address/Data bus · 64 K-Byte SRAM · 3 Removable Media Interfaces [MMC/SD/SDIO] ­ IO Voltage: · mDDR/DDR2 IOs: 1. 8V · Other IOs: 1. 8V and 3. 3V ­ Core Voltage: 1. 2V ­ Commercial and Industrial Temperature Grade (operating restrictions apply) ­ 16-bit Video Input Port capable of capturing HD video ­ HD resolution Display Subsystem ­ Serial Communication · High-End CAN Controller · 10/100 Mbit Ethernet MAC · USB OTG subsystem with standard DP/DM interface [HS/FS/LS] · Multiport USB Host Subsystem [HS/FS/LS] ­ 12-pin ULPI or 6/4/3-pin Serial Interface · Four Master/Slave Multichannel Serial Port Interface (McSPI) Ports · Five Multichannel Buffered Serial Ports ­ 512-Byte Transmit/Receive Buffer (McBSP1/3/4/5) ­ 5K-Byte Transmit/Receive Buffer 1 2 3 4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All other trademarks are the property of their respective owners. Copyright © 2009­2010, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. AM3517, AM3505 SPRS550B ­ OCTOBER 2009 ­ REVISED JULY 2010 www. ti. com · · · · · ­ Built-in Digital Clamping and Black Level Compensation ­ 10-bit to 8-bit A-law Compression Hardware ­ Supports up to 16K Pixels (Image Size) in Horizontal and Vertical Directions System Direct Memory Access (sDMA) Controller (32 Logical Channels With Configurable Priority) Comprehensive Power, Reset and Clock Management ARM CortexTM-A8 Memory Architecture ­ ARMv7 Architecture · TrustZone ® · Thumb ®-2 · MMU Enhancements ­ In-Order, Dual-Issue, Superscalar Microprocessor Core ­ NEONTM Multimedia Architecture ­ Over 2x Performance of ARMv6 SIMD ­ Supports Both Integer and Floating Point SIMD ­ Jazelle ® RCT Execution Environment Architecture ­ Dynamic Branch Prediction with Branch Target Address Cache, Global history buffer and 8 entry return stack ­ Embedded Trace Macrocell [ETM] support for Non_invasive Debug ­ 16K-Byte instruction Cache (4-Way setassociative) ­ 16K-Byte Data Cache (4-Way Set-Associative) ­ 256K-Byte L2 Cache POWERVR SGXTM Graphics Accelerator ­ Tile Based Architecture Delivering up to 10 MPoly/sec ­ Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality ­ Industry Standard API Support: OpenGLES 1. 1 and 2. 0, OpenVG1. 0 ­ Fine Grained Task Switching, Load Balancing, and Power Management ­ Programmable, High-Quality Image Anti-Aliasing Endianess · · · · · · ­ ARM Instructions - Little Endian ­ ARM Data ­ Configurable SDRC Memory Controller ­ 16/32-bit Memory Controller With 1G-Byte Total Address Space ­ Double Data Rate (DDR2) SDRAM, mobile Double Data Rate (mDDR)SDRAM ­ SDRAM Memory Scheduler (SMS) and Rotation Engine General Purpose Memory Controller (GPMC) ­ 16-bit Wide Multiplexed Address/Data Bus ­ Up to 8 Chip Select Pins With 128M-Byte Address Space per Chip Select Pin ­ Glueless Interface to NOR Flash, NAND Flash (With ECC Hamming Code Calculation), SRAM and Pseudo-SRAM ­ Flexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, etc. ) ­ Nonmultiplexed Address/Data Mode (Limited 2K-Byte Address Space) Test Interfaces ­ IEEE-1149. 1 (JTAG) Boundary-Scan Compatible ­ Embedded Trace Macro Interface (ETM) 65-nm CMOS technology Packages: ­ 491-pin BGA (17x17, 0. 65mm pitch) [ZCN suffix] with via channel array technology ­ 484-pin PBGA (23x23, 1mm pitch) [ZER suffix] Applications: ­ Single Board Computers ­ Industrial and Home Automation ­ Digital Signage ­ Point of Service ­ Portable Media Player ­ Portable Industrial ­ Transportation ­ Navigation ­ Smart White Goods ­ Digital TV ­ Digital Video Camera ­ Gaming 2 AM3517/05 ARM Microprocessor Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 Copyright © 2009­2010, Texas Instruments Incorporated AM3517, AM3505 www. ti. com SPRS550B ­ OCTOBER 2009 ­ REVISED JULY 2010 1. 2 Description AM3517/05 high-performance, industrial applications processors with video, image, and graphics processing sufficient to support the following: · Single Board Computers · Home and Industrial automation · Digital Signage The device supports high-level operating systems (OSs), such as: · Linux · Windows CE The following subsystems are part of the device: · Microprocessor unit (MPU) subsystem based on the ARM Cortex-A8 microprocessor · POWERVR SGXTM Graphics Accelerator (AM3517 Device only) Subsystem for 3D graphics acceleration to support display and gaming effects (AM3517 only) · Display subsystem with several features for multiple concurrent image manipulation, and a programmable interface supporting a wide variety of displays. [. . . ] Generally, the DDR2 interface is compatible with x16 or x32 DDR2 speed grade DDR2-333 devices. 1 2 3 4 (1) (2) (3) Parameter JEDEC DDR2 Device Speed Grade JEDEC DDR2 Device Bit Width JEDEC DDR2 Device Count JEDEC DDR2 Device Ball Count Min DDR2-333 MHz x16 1 84 x32 2 92 Bits Devices Balls See Note See Note (2) (3) Max Unit Notes See Note (1) Higher DDR2 speed grades operating at the specified speeds are supported due to inherent JEDEC DDR2 backwards compatibility. If a package contains 2 dies, that is the maximum number of devices that can be connected. Electrically, the 92 and 84 ball DDR2 devices are the same. Copyright © 2009­2010, Texas Instruments Incorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 137 AM3517, AM3505 SPRS550B ­ OCTOBER 2009 ­ REVISED JULY 2010 www. ti. com 6. 4. 2. 2. 3 PCB Stackup The minimum stackup required for routing the AM3517/05 is a six layer stack as shown in Table 6-23. Additional layers may be added to the PCB stack up to accommodate other circuitry or to reduce the size of the PCB footprint. Minimum PCB Stack Up Layer 1 2 3 4 5 6 Type Signal Plane Plane Signal Plane Signal Description Top Routing Mostly Horizontal Ground Power Internal Routing Ground Bottom Routing Mostly Vertical 138 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Copyright © 2009­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 AM3517, AM3505 www. ti. com SPRS550B ­ OCTOBER 2009 ­ REVISED JULY 2010 Complete stack up specifications are provided in Table 6-24. AM35x SDRC_D0 SDRC_D7 SDRC_DM0 SDRC_DQS0P SDRC_DQS0N SDRC_D8 T DQ0 DQ7 LDM LDQS LDQS# LQ8 LQ15 UDM UDQS UDQS# Length = avg DQS0-1 length+CLK T T T T T SDRC_D15 SDRC_DM1 SDRC_DQS1P SDRC_DQS1N SDRC_STRBEN0 SDRC_STRBEN_DLY0 T T T T T x16 DDR2 DQ0 DQ7 LDM LDQS LDQS# DQ8 DQ15 UDM UDQS UDQS# SDRC_D16 SDRC_D23 SDRC_DM2 SDRC_DQS2P SDRC_DQS2N SDRC_D24 SDRC_D31 SDRC_DM3 SDRC_DQS3P SDRC_DQS3N SDRC_STRBEN1 SDRC_STRBEN_DLY1 T T T T T T T T T T T Length = avg DQS2-3 length+CLK T T T T SDRC_BA0 SDRC_BA1 SDRC_BA2 SDRC_A0 SDRC_A14 SDRC_nCS0 SDRC_nCS1 SDRC_nCAS SDRC_nRAS SDRC_nWE SDRC_nCKE0 SDRC_CLK SDRC_nCLK SDRC_ODT VREFSSTL DDR_PADREF BA0 BA1 BA2* A0 A14* CS1 CS2* CAS# RAS# WE# CLK CLK# ODT* VREF BA0 BA1 BA2* A0 A14* CS1 CS2* CAS# RAS# WE# CLK CLK# ODT* VREF (A) 0. 1mF T T T T T T T T T T Vio1. 8 0. 1mF 1K W 1% 0. 1mF(A) 0. 1mF(A) 0. 1mF 1K W 1% 50 1% SPRS550-008 A. See VREF Routing and Topology figure for information on capacitor placement. Figure 6-23. DDR2 Dual-Memory High Level Schematic Copyright © 2009­2010, Texas Instruments Incorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 139 AM3517, AM3505 SPRS550B ­ OCTOBER 2009 ­ REVISED JULY 2010 www. ti. com AM35x SDRC_D0 SDRC_D7 SDRC_DM0 SDRC_DQS0P SDRC_DQS0N SDRC_D8 SDRC_D15 SDRC_DM1 SDRC_DQS1P SDRC_DQS1N SDRC_STRBEN0 SDRC_STRBEN_DLY0 T DDR2 DQ0 DQ7 DM0 DQS0 DQS0# DQ8 DQ15 DM1 DQS1 DQS1# Length = avg D0-D15 length+CLK T T T T T T T T T T SDRC_D16 SDRC_D23 SDRC_DM2 SDRC_DQS2P SDRC_DQS2N SDRC_D24 SDRC_D31 SDRC_DM3 SDRC_DQS3P SDRC_DQS3N SDRC_STRBEN1 SDRC_STRBEN_DLY1 T DQ16 DQ23 DM2 DQS2 DQS2# DQ24 DQ31 DM3 DQS3 DQS3# Length = avg D16-D31 length+CLK T T T T T T T T T T T T T T SDRC_BA0 SDRC_BA1 SDRC_BA2 SDRC_A0 SDRC_A14 SDRC_nCS0 SDRC_nCS1 SDRC_nCAS SDRC_nRAS SDRC_nWE SDRC_nCKE0 SDRC_CLK SDRC_nCLK SDRC_ODT VREFSSTL DDR_PADREF BA0 BA1 BA2* A0 A14* CS1 CS2* CAS# RAS# WE# CKE CLK CLK# ODT* VREF T T T T T T T T T T Vio1. 8 0. 1mF 1K W 1% 0. 1mF (A) 0. 1mF (A) 0. 1mF (A) 0. 1mF 1K W 1% 50 1% SPRS550-009 A. See VREF Routing and Topology figure for information on capacitor placement. Figure 6-24. DDR2 Single-Memory High Level Schematic 140 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Copyright © 2009­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 AM3517, AM3505 www. ti. com SPRS550B ­ OCTOBER 2009 ­ REVISED JULY 2010 Table 6-24. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (1) (2) (3) Parameter PCB Routing/Plane Layers Signal Routing Layers Full ground layers under DDR2 routing Region Number of ground plane cuts allowed within DDR routing region Number of ground reference planes required for each DDR2 routing layer Number of layers between DDR2 routing layer and ground plane PCB Routing Feature Size PCB Trace Width w PCB BGA escape via pad size PCB BGA escape via hole size AM3517/05 BGA pad size DDR2 Device BGA pad size Single Ended Impedance, Zo Impedance Control 50 Z-5 Z 75 Z+5 See Note (3) Min 6 3 2 Typ Max Unit Notes 0 1 0 4 4 20 10 12 Mils Mils Mils Mils See Note See Note (1) (2) The recommended pad size is 0. 3 mm per IPC-7351 specification. Please refer to IPC standard IPC-7351 or manufacturer's recommendations for correct BGA pad size. Z is the nominal singled ended impedance selected for the PCB specified by item 12. 6. 4. 2. 2. 4 Placement Figure 6-24 shows the required placement for the DDR2 devices. The placement does not restrict the side of the PCB that the devices are mounted on. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space. For single-memory DDR2 systems, the second DDR2 device is omitted from the placement. X A1 Y OFFSET Y DDR2 Device Y OFFSET A1 Recommended DDR2 Device Orientation DDR2 Controller AM3517/05 Figure 6-25. DDR2 Device Placement Copyright © 2009­2010, Texas Instruments Incorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 141 AM3517, AM3505 SPRS550B ­ OCTOBER 2009 ­ REVISED JULY 2010 www. ti. com Table 6-25. 1 2 3 4 5 (1) (2) (3) (4) (5) Parameter X Y Y Offset DDR2 Keepout Region Clearance from non-DDR2 signal to DDR2 Keepout Region 4 w Min Max 1750 1280 650 Unit Mils Mils Mils Notes See Notes See Notes See Notes (3) (1) (2) , (1) (2) , (1) (2) . , See Note See Note (4) (5) See Figure 6-23 for dimension definitions. Measurements from center of AM3517/05 device to center of DDR2 device. For single memory systems it is recommended that Y Offset be as small as possible. DDR2 Keepout region to encompass entire DDR2 routing area Non-DDR2 signals allowed within DDR2 keepout region provided they are separated from DDR2 routing layers by a ground plane. 6. 4. 2. 2. 5 DDR2 Keep Out Region The region of the PCB used for the DDR2 circuitry must be isolated from other signals. The DDR2 keep out region is defined for this purpose and is shown in Figure 6-26. [. . . ] In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. [. . . ]