User manual TEXAS INSTRUMENTS AM3715 DATA MANUAL REV B

[. . . ] AM3715/03 www. ti. com SPRS616B ­ JUNE 2010 ­ REVISED JULY 2010 AM3715/03 Applications Processor 1 AM3715/03 Applications Processor 1. 1 1234 Features ­ 1. 8-V I/O and 3. 0-V (MMC1 only), 0. 9-V to 1. 2-V Adaptive Processor Core Voltage 0. 9-V to 1. 1-V Adaptive Core Logic Voltage Note: These are default Operating Performance Point (OPP) voltages and could be optimized to lower values using SmartReflex AVS. ­ Commercial and Extended Temperature Grades ­ Serial Communication · 5 Multichannel Buffered Serial Ports (McBSPs) ­ 512 Byte Transmit/Receive Buffer (McBSP1/3/4/5) ­ 5K-Byte Transmit/Receive Buffer (McBSP2) ­ SIDETONE Core Support (McBSP2 and 3 Only) For Filter, Gain, and Mix Operations ­ Direct Interface to I2S and PCM Device and T Buses ­ 128 Channel Transmit/Receive Mode · Four Master/Slave Multichannel Serial Port Interface (McSPI) Ports · High-Speed/Full-Speed/Low-Speed USB OTG Subsystem (12-/8-Pin ULPI Interface) · High-Speed/Full-Speed/Low-Speed Multiport USB Host Subsystem ­ 12-/8-Pin ULPI Interface or 6-/4-/3-Pin Serial Interface · One HDQ/1-Wire Interface · Four UARTs (One with Infrared Data Association [IrDA] and Consumer Infrared [CIR] Modes) · Three Master/Slave High-Speed Inter-Integrated Circuit (I2C) Controllers ­ Camera Image Signal Processing (ISP) · CCD and CMOS Imager Interface · Memory Data Input · BT. 601/BT. 656 Digital YCbCr 4:2:2 (8-/10-Bit) Interface · AM3715/03 Applications Processor: ­ Compatible with OMAPTM 3 Architecture ­ MPU Subsystem · 1-GHz ARM CortexTM-A8 Core · NEON SIMD Coprocessor ­ POWERVR SGXTM Graphics Accelerator (AM3715 only) · Tile Based Architecture Delivering up to 20 MPoly/sec · Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality · Industry Standard API Support: OpenGLES 1. 1 and 2. 0, OpenVG1. 0 · Fine Grained Task Switching, Load Balancing, and Power Management · Programmable High Quality Image Anti-Aliasing ­ External Memory Interfaces: · SDRAM Controller (SDRC) ­ 16, 32-bit Memory Controller With 1G-Byte Total Address Space ­ Interfaces to Low-Power SDRAM ­ SDRAM Memory Scheduler (SMS) and Rotation Engine · General Purpose Memory Controller (GPMC) ­ 16-bit Wide Multiplexed Address/Data Bus ­ Up to 8 Chip Select Pins With 128M-Byte Address Space per Chip Select Pin ­ Glueless Interface to NOR Flash, NAND Flash (With ECC Hamming Code Calculation), SRAM and Pseudo-SRAM ­ Flexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, etc. ) ­ Nonmultiplexed Address/Data Mode (Limited 2K-Byte Address Space) 1 2 3 4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All other trademarks are the property of their respective owners. Copyright © 2010, Texas Instruments Incorporated PRODUCT PREVIEW information concerns products in the formative or design phase of development. Texas Instruments reserves the right to change or discontinue these products without notice. PRODUCT PREVIEW AM3715/03 SPRS616B ­ JUNE 2010 ­ REVISED JULY 2010 www. ti. com ­ ­ ­ ­ Glueless Interface to Common Video Decoders · Resize Engine ­ Resize Images From 1/4x to 4x ­ Separate Horizontal/Vertical Control System Direct Memory Access (SDMA) Controller (32 Logical Channels With Configurable Priority) Comprehensive Power, Reset, and Clock Management · SmartReflexTM Technology · Dynamic Voltage and Frequency Scaling (DVFS) ARM CortexTM-A8 Core · ARMv7 Architecture ­ Trust Zone ­ Thumb®-2 ­ MMU Enhancements · In-Order, Dual-Issue, Superscalar Microprocessor Core · NEON Multimedia Architecture · Over 2x Performance of ARMv6 SIMD · Supports Both Integer and Floating Point SIMD · Jazelle® RCT Execution Environment Architecture · Dynamic Branch Prediction with Branch Target Address Cache, Global History Buffer, and 8-Entry Return Stack · Embedded Trace Macrocell (ETM) Support for Non-Invasive Debug ARM Cortex-A8 Memory Architecture: · 32K-Byte Instruction Cache (4-Way · · · · · · · · · · · Set-Associative) 32K-Byte Data Cache (4-Way Set-Associative) · 256K-Byte L2 Cache ­ 32K-Byte ROM ­ 64K-Byte Shared SRAM ­ Endianess: · ARM Instructions - Little Endian · ARM Data ­ Configurable Removable Media Interfaces: ­ Three Multimedia Card (MMC)/ Secure Digital (SD) With Secure Data I/O (SDIO) Test Interfaces ­ IEEE-1149. 1 (JTAG) Boundary-Scan Compatible ­ Embedded Trace Macro Interface (ETM) ­ Serial Data Transport Interface (SDTI) 12 32-bit General Purpose Timers 2 32-bit Watchdog Timers 1 32-bit Secure Watchdog Timer 1 32-bit 32-kHz Sync Timer Up to 188 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions) 45-nm CMOS Technology Package-On-Package (POP) Implementation for Memory Stacking Packages: ­ 515-pin s-PBGA package (CBP Suffix), . 5mm Ball Pitch (Top), . 4mm Ball Pitch (Bottom) ­ 515-pin s-PBGA package (CBC Suffix), . 65mm Ball Pitch (Top), . 5mm Ball Pitch (Bottom) ­ 423-pin s-PBGA package (CUS Suffix) · PRODUCT PREVIEW 2 AM3715/03 Applications Processor Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated AM3715/03 www. ti. com SPRS616B ­ JUNE 2010 ­ REVISED JULY 2010 1. 2 Description The AM37x family of high-performance, applications processors are based on the enhanced device architecture and are integrated on TI's advanced 45-nm process technology. [. . . ] (2) P = cam_xclkn(4) period in ns (3) The jitter probability density can be approximated by a Gaussian function. (4) In cam_xclkn, n is equal to a or b. 5. 5. 1. 2 Parallel Camera Interface (CPI) 5. 5. 1. 2. 1 CPI--Video and Graphics Digitizer 1. 8V Mode The imaging subsystem deals with the processing of the pixel data coming from an external image sensor or from video and graphics digitizer. It is a key component for the following multimedia applications: video preview, camera viewfinder, video record and still image capture. It supports RAW, RGB, and YUV data processing. Copyright © 2010, Texas Instruments Incorporated Timing Requirements and Switching Characteristics Submit Documentation Feedback 171 PRODUCT PREVIEW AM3715/03 SPRS616B ­ JUNE 2010 ­ REVISED JULY 2010 www. ti. com Table 5-18 assumes testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 5-19 and Figure 5-20). CPI Timing Conditions--Video and Graphics Digitizer 1. 8-V Mode TIMING CONDITION PARAMETER MIN Input Conditions tR tF Input signal rise time Input signal fall time 80 80 1800 1800 ps ps VALUE MAX UNIT Table 5-18. CPI Timing Requirements--Video and Graphics Digitizer 1. 8-V Mode(4) (6) NO. ISP1 ISP2 ISP3 1 / tc(pclk) tw(pclkL) tw(pclkH) tdc(pclk) PARAMETER Frequency(1), input pixel clock cam_pclk Typical pulse duration, input pixel clock cam_pclk low Typical pulse duration, input pixel clock cam_pclk high Duty cycle error, input pixel clock cam_pclk Cycle jitter(3), input pixel clock cam_pclk Setup time, input vertical synchronization cam_vs valid before input pixel clock cam_pclk rising/falling edge Hold time, input vertical synchronization cam_vs valid after input pixel clock cam_pclk rising/falling edge Setup time, input horizontal synchronization cam_hs valid before input pixel clock cam_pclk rising/falling edge Hold time, input horizontal synchronization cam_hs valid after input pixel clock cam_pclk rising/falling edge Setup time, input data cam_d[n:0](5) valid before input pixel clock cam_pclk rising/falling edge Hold time, input data cam_d[n:0](5) valid after input pixel clock cam_pclk rising/falling edge Setup time, input write enable cam_wen valid before input pixel clock cam_pclk rising/falling edge Hold time, input write enable cam_wen valid after input pixel clock cam_pclk rising/falling edge Setup time, input field identification cam_fld valid before input pixel clock cam_pclk rising/falling edge Hold time, input field identification cam_fld valid after input pixel clock cam_pclk rising/falling edge 0. 75 0. 96 0. 75 0. 96 0. 75 0. 96 0. 75 0. 96 0. 75 0. 96 0. 5P (2) OPP100 MIN MAX 148. 5 0. 5P(2) 0. 5*P(2) 3. 247 0. 06P(2) UNIT MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns PRODUCT PREVIEW tJ(pclk) ISP4 ISP5 ISP6 ISP7 ISP8 ISP9 ISP10 ISP11 ISP12 ISP13 tsu(vsV-pclkH) th(pclkH-vsV) tsu(hsV-pclkH) th(pclkH-hsV) tsu(dV-pclkH) th(pclkH-dV) tsu(wenV-pclkH) th(pclkH-wenV) tsu(fldV-pclkH) th(pclkH-fldV) (1) Related with the input maximum frequency supported by the ISP module in 8-bit mode with 8 to 16 data bits conversion bridge enabled. (2) P = cam_pclk period in ns (3) Maximum cycle jitter supported by cam_pclk input clock (4) The timing requirements are assured up to the cycle jitter and duty cycle error conditions specified. (6) See Operating Condition Addendum for OPP voltages. 172 Timing Requirements and Switching Characteristics Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated AM3715/03 www. ti. com SPRS616B ­ JUNE 2010 ­ REVISED JULY 2010 ISP3 ISP1 cam_pclk ISP2 ISP4 cam_vs ISP5 ISP6 cam_hs ISP7 ISP8 ISP9 cam_d[N:0] D(0) D(n-2) D(n-1) D(0) D(n-2) D(n-1) ISP10 cam_wen ISP11 cam_fld SWPS038-048 (1) (2) The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are software configurable. Optionally, the cam_wen signal can be used as an external memory write-enable signal. When the number of data lines is less than cam_d[N:0], data lines can be connected to the upper or lower lines of cam_d[N:0]. For more information about video port mapping, see the AM3715/03 TRM. Figure 5-19. CPI--Video and Graphics Digitizer--1. 8-V Progressive Mode Copyright © 2010, Texas Instruments Incorporated Timing Requirements and Switching Characteristics Submit Documentation Feedback 173 PRODUCT PREVIEW AM3715/03 SPRS616B ­ JUNE 2010 ­ REVISED JULY 2010 www. ti. com ISP3 ISP1 cam_pclk ISP2 ISP4 cam_vs ISP6 cam_hs ISP5 ISP7 ISP8 ISP9 cam_d[N:0] D(0) D(n­1) D(0) D(n­1) D(0) D(n­1) D(0) D(n­1) ISP10 cam_wen ISP12 cam_fld EVEN ISP13 ISP11 PRODUCT PREVIEW ODD SWPS038-049 (1) (2) The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are software configurable. Optionally, the cam_wen signal can be used as an external memory write-enable signal. When the number of data lines is less than cam_d[N:0], data lines can be connected to the upper or lower lines of cam_d[N:0]. For more information about video port mapping, see the AM3715/03 TRM. Figure 5-20. CPI--Video and Graphics Digitizer--1. 8-V Interlaced Mode 5. 5. 1. 2. 2 CPI--12-Bit SYNC Normal Progressive Mode Table 5-20 assumes testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 5-21). CPI Timing Conditions--12-Bit SYNC Normal Progressive Mode(1) TIMING CONDITION PARAMETER Input Conditions tR tF CLOAD Input signal rise time Input signal fall time Output load capacitance 2. 7 2. 7 8. 6 ns ns pF VALUE UNIT Output Condition (1) The load setting of the IO buffer: LB0 = 1. 174 Timing Requirements and Switching Characteristics Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated AM3715/03 www. ti. com SPRS616B ­ JUNE 2010 ­ REVISED JULY 2010 Table 5-20. CPI Timing Requirements--12-Bit SYNC Normal Progressive Mode(4) (5) NO. ISP17 ISP18 ISP18 1 / tc(pclk) tw(pclkH) tw(pclkL) tdc(pclk) tJ(pclk) ISP19 ISP20 ISP21 ISP22 ISP23 ISP24 ISP25 ISP26 tsu(dV-pclkH) th(pclkH-dV) tsu(dV-vsH) th(pclkH-vsV) tsu(dV-hsH) th(pclkH-hsV) tsu(dV-hsH) th(pclkH-hsV) PARAMETER Frequency(1), input pixel clock cam_pclk Typical pulse duration, input pixel clock cam_pclk high Typical pulse duration, input pixel clock cam_pclk low Duty cycle error, input pixel clock cam_pclk Cycle jitter(3), input pixel clock cam_pclk Setup time, input data cam_d[11:0] valid before input pixel clock cam_pclk rising edge Hold time, input data cam_d[11:0] valid after input pixel clock cam_pclk rising edge Setup time, input vertical synchronization cam_vs valid before input pixel clock cam_pclk rising edge Hold time, input vertical synchronization cam_vs valid after input pixel clock cam_pclk rising edge Setup time, input horizontal synchronization cam_hs valid before input pixel clock cam_pclk rising edge Hold time, input horizontal synchronization cam_hs valid after input pixel clock cam_pclk rising edge Setup time, input write enable cam_wen valid before input pixel clock cam_pclk rising edge Hold time, input write enable cam_wen valid after input pixel clock cam_pclk rising edge 1. 82 1. 82 1. 82 1. 82 1. 82 1. 82 1. 82 1. 82 0. 5P(2) 0. 5P (2) OPP100 MIN MAX 75 OPP50 MIN MAX 45 0. 5P(2) 0. 5P (2) UNIT MHz ns ns ns ns ns ns ns ns ns ns ns ns 0. 5P(2) 3. 465 0. 0649*P (2) 0. 5P(2) 6. 93 0. 0649*P (2) 3. 25 3. 25 3. 25 3. 25 3. 25 3. 25 3. 25 3. 25 (1) Related with the input maximum frequency supported by the ISP module. (2) P = cam_pclk period in ns (3) Maximum cycle jitter supported by cam_pclk input clock. (4) The timing requirements are assured up to the cycle jitter and duty cycle error conditions specified. [. . . ] In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. [. . . ]