User manual TEXAS INSTRUMENTS DM3730 PRODUCT PREVIEW 08-2010

[. . . ] DM3730, DM3725 www. ti. com SPRS685A ­ AUGUST 2010 ­ REVISED SEPTEMBER 2010 DM3730, DM3725 Digital Media Processor Check for Samples: DM3730, DM3725 1 DM3730, DM3725 Digital Media Processor 1. 1 12345 Features All Instructions Conditional Additional C64x+TM Enhancements ­ Protected Mode Operation ­ Expectations Support for Error Detection and Program Redirection ­ Hardware Support for Modulo Loop Operation ­ C64x+TM L1/L2 Memory Architecture · 32K-Byte L1P Program RAM/Cache (Direct Mapped) · 80K-Byte L1D Data RAM/Cache (2-Way Set- Associative) · 64K-Byte L2 Unified Mapped RAM/Cache (4- Way Set-Associative) · 32K-Byte L2 Shared SRAM and 16K-Byte L2 ROM ­ C64x+TM Instruction Set Features · Byte-Addressable (8-/16-/32-/64-Bit Data) · 8-Bit Overflow Protection · Bit-Field Extract, Set, Clear · Normalization, Saturation, Bit-Counting · Compact 16-Bit Instructions · Additional Instructions to Support Complex Multiplies ­ External Memory Interfaces: · SDRAM Controller (SDRC) ­ 16, 32-bit Memory Controller With 1G-Byte Total Address Space ­ Interfaces to Low-Power SDRAM ­ SDRAM Memory Scheduler (SMS) and Rotation Engine · General Purpose Memory Controller (GPMC) ­ 16-bit Wide Multiplexed Address/Data Bus ­ Up to 8 Chip Select Pins With 128M-Byte Address Space per Chip Select Pin ­ Glueless Interface to NOR Flash, · · · DM3730/25 Digital Media Processor: ­ Compatible with OMAPTM 3 Architecture ­ ARM® microprocessor (MPU) Subsystem · Up to 1-GHz ARM® CortexTM-A8 Core See Processor Clocks OPP table. · NEON SIMD Coprocessor ­ High Performance Image, Video, Audio (IVA2. 2TM) Accelerator Subsystem · Up to 800-MHz TMS320C64x+TM DSP Core · Enhanced Direct Memory Access (EDMA) Controller (128 Independent Channels) · Video Hardware Accelerators ­ POWERVR SGXTM Graphics Accelerator (DM3730 only) · Tile Based Architecture Delivering up to 20 MPoly/sec · Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality · Industry Standard API Support: OpenGLES 1. 1 and 2. 0, OpenVG1. 0 · Fine Grained Task Switching, Load Balancing, and Power Management · Programmable High Quality Image Anti-Aliasing ­ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+TM DSP Core · Eight Highly Independent Functional Units · Six ALUs (32-/40-Bit); Each Supports Single 32- bit, Dual 16-bit, or Quad 8-bit, Arithmetic per Clock Cycle · Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle · Load-Store Architecture With Non-Aligned Support · 64 32-Bit General-Purpose Registers · Instruction Packing Reduces Code Size 1 2 3 4 5 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. ARM is a registered trademark of ARM Ltd. Copyright © 2010, Texas Instruments Incorporated PRODUCT PREVIEW information concerns products in the formative or design phase of development. Texas Instruments reserves the right to change or discontinue these products without notice. PRODUCT PREVIEW DM3730, DM3725 SPRS685A ­ AUGUST 2010 ­ REVISED SEPTEMBER 2010 www. ti. com ­ ­ ­ ­ NAND Flash (With ECC Hamming Code Calculation), SRAM and Pseudo-SRAM ­ Flexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, etc. ) ­ Nonmultiplexed Address/Data Mode (Limited 2K-Byte Address Space) 1. 8-V I/O and 3. 0-V (MMC1 only), 0. 9-V to 1. 2-V Adaptive Processor Core Voltage 0. 9-V to 1. 1-V Adaptive Core Logic Voltage Note: These are default Operating Performance Point (OPP) voltages and could be optimized to lower values using SmartReflex AVS. [. . . ] DQS and DQ Routing Specification (1) PRODUCT PREVIEW PARAMETER DQS E Skew Length Mismatch Center to Center DQS to other LPDDR trace spacing DQS/DQ nominal trace length DQ to DQS Skew Length Mismatch DQ to DQ Skew Length Mismatch Center to Center DQ to other LPDDR trace spacing Center to Center DQ to other DQ trace spacing DQ E Skew Length Mismatch (1) (2) (3) (4) (5) MIN TYP MAX 25 UNIT Mils NOTES 4w DQLM - 50 DQLM DQLM + 50 100 100 4w 3w 100 Mils Mils Mils Mils See Note (2) See Note (2) See Note See Note (3) (3) See Note (4) See Note (2), (5) Series terminator, if used, should be located closest to LPDDR. Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion. There is no need, and it is not recommended, to skew match across data bytes. DQLM is the longest Manhattan distance of the DQS and DQ net classes. 178 Timing Requirements and Switching Characteristics Submit Documentation Feedback Product Folder Link(s): DM3730 DM3725 Copyright © 2010, Texas Instruments Incorporated DM3730, DM3725 www. ti. com SPRS685A ­ AUGUST 2010 ­ REVISED SEPTEMBER 2010 5. 5 5. 5. 1 Multimedia Interfaces Camera ISP2P Interface NOTE For more information, see Camera ISP chapter of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4). The camera subsystem provides the system interfaces and the processing capability to connect raw, YUV or JPEG image sensor modules to the device for video-preview, video-record and still-image-capture applications. The camera ISP2P subsystem supports up to two simultaneous pixel flows but only one of them can use the video processing hardware: · Parallel camera interface + Serial camera interface: one interface data goes through the video processing hardware. The other interface data goes directly to memory · Serial camera interface + Serial camera interface: one serial interface data goes through the video processing hardware. The other serial interface data goes directly to memory. Note: For more information, see the Camera ISP / Camera ISP Environment / Camera ISP Connectivity Schemes section of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4). ISP2P cam_xclka and cam_xclkb Output Clocks Switching Characteristics NO. ISP15 ISP16 ISP16 1 / tc(xclk) tw(xclkH) tw(xclkL) tdc(xclk) tJ(xclk) tR(xclk) tF(xclk) PARAMETER MIN Frequency(1), output clock cam_xclkn(4) Typical pulse duration, output clock cam_xclkn(4) high Typical pulse duration, output clock cam_xclkn(4) low Duty cycle error, output clock cam_xclkn(4) Cycle jitter , output clock cam_xclkn Rise time, output clock cam_xclkn(4) Fall time, output clock cam_xclkn(4) (4) (3) (4) OPP100 MAX 216 0. 5P(2) 0. 5P(2) 0. 5 * P(2) - 2. 083 0. 044 * P 0. 93 0. 93 (2) OPP50 MIN MAX 216 0. 5P(2) 0. 5P(2) 0. 5 * P(2) - 2. 083 0. 044 * P(2) 0. 93 0. 93 UNIT MHz ns ns ps ps ns ns (1) Related with the cam_xclkn maximum and minimum frequencies programmable in the ISP module. NOTE: You must disable the camera sensor or the camera module to change the frequency configuration. For more information, see the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4). (2) P = cam_xclkn(4) period in ns (3) Maximum cycle jitter supported by cam_xclka and cam_xclkb output clocks. (4) In cam_xclkn, n is equal to a or b. Copyright © 2010, Texas Instruments Incorporated Timing Requirements and Switching Characteristics Submit Documentation Feedback Product Folder Link(s): DM3730 DM3725 179 PRODUCT PREVIEW The camera ISP2P subsystem supports different camera configurations: · 10-bit Parallel interface · 12-bit Parallel interface · 12-bit Parallel interface DM3730, DM3725 SPRS685A ­ AUGUST 2010 ­ REVISED SEPTEMBER 2010 www. ti. com 5. 5. 1. 2 Parallel Camera Interface (CPI) 5. 5. 1. 2. 1 CPI--Video and Graphics Digitizer 1. 8V Mode The imaging subsystem deals with the processing of the pixel data coming from an external image sensor or from video and graphics digitizer. It is a key component for the following multimedia applications: video preview, camera viewfinder, video record and still image capture. Table 5-24 assumes testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 5-23 and Figure 5-24). CPI Timing Conditions--Video and Graphics Digitizer 1. 8-V Mode TIMING CONDITION PARAMETER MIN Input Conditions tR tF Input signal rise time Input signal fall time 80 80 1800 1800 ps ps VALUE MAX UNIT Table 5-24. CPI Timing Requirements--Video and Graphics Digitizer 1. 8-V Mode(4) (6) PRODUCT PREVIEW 180 NO. ISP1 ISP2 ISP3 1 / tc(pclk) tw(pclkL) tw(pclkH) tdc(pclk) tJ(pclk) ISP4 ISP5 ISP6 ISP7 ISP8 ISP9 ISP10 ISP11 ISP12 ISP13 tsu(vsV-pclkH) th(pclkH-vsV) tsu(hsV-pclkH) th(pclkH-hsV) tsu(dV-pclkH) th(pclkH-dV) tsu(wenV-pclkH) th(pclkH-wenV) tsu(fldV-pclkH) th(pclkH-fldV) PARAMETER Frequency(1), input pixel clock cam_pclk Typical pulse duration, input pixel clock cam_pclk low Typical pulse duration, input pixel clock cam_pclk high Duty cycle error, input pixel clock cam_pclk Cycle jitter(3), input pixel clock cam_pclk Setup time, input vertical synchronization cam_vs valid before input pixel clock cam_pclk rising/falling edge Hold time, input vertical synchronization cam_vs valid after input pixel clock cam_pclk rising/falling edge Setup time, input horizontal synchronization cam_hs valid before input pixel clock cam_pclk rising/falling edge Hold time, input horizontal synchronization cam_hs valid after input pixel clock cam_pclk rising/falling edge Setup time, input data cam_d[n:0](5) valid before input pixel clock cam_pclk rising/falling edge Hold time, input data cam_d[n:0](5) valid after input pixel clock cam_pclk rising/falling edge Setup time, input write enable cam_wen valid before input pixel clock cam_pclk rising/falling edge Hold time, input write enable cam_wen valid after input pixel clock cam_pclk rising/falling edge Setup time, input field identification cam_fld valid before input pixel clock cam_pclk rising/falling edge Hold time, input field identification cam_fld valid after input pixel clock cam_pclk rising/falling edge OPP100 MIN 0. 5P (2) UNIT MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns MAX 148. 5 0. 5P(2) 0. 5*P(2) 3. 247 0. 06P(2) 0. 75 0. 96 0. 75 0. 96 0. 75 0. 96 0. 75 0. 96 0. 75 0. 96 (1) Related with the input maximum frequency supported by the ISP module in 8-bit mode with 8 to 16 data bits conversion bridge enabled. (2) P = cam_pclk period in ns (3) Maximum cycle jitter supported by cam_pclk input clock (4) The timing requirements are assured up to the cycle jitter and duty cycle error conditions specified. Timing Requirements and Switching Characteristics Submit Documentation Feedback Product Folder Link(s): DM3730 DM3725 Copyright © 2010, Texas Instruments Incorporated DM3730, DM3725 www. ti. com SPRS685A ­ AUGUST 2010 ­ REVISED SEPTEMBER 2010 ISP3 ISP1 cam_pclk ISP2 ISP4 cam_vs ISP5 ISP6 cam_hs ISP7 ISP8 ISP9 cam_d[N:0] D(0) D(n-2) D(n-1) D(0) D(n-2) D(n-1) ISP10 cam_wen ISP11 cam_fld SWPS038-048 (1) (2) The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are software configurable. Optionally, the cam_wen signal can be used as an external memory write-enable signal. For further details, see the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4). [. . . ] Device Nomenclature Package Characteristics Submit Documentation Feedback Product Folder Link(s): DM3730 DM3725 Copyright © 2010, Texas Instruments Incorporated DM3730, DM3725 www. ti. com SPRS685A ­ AUGUST 2010 ­ REVISED SEPTEMBER 2010 6. 3 Mechanical Data Copyright © 2010, Texas Instruments Incorporated Package Characteristics Submit Documentation Feedback Product Folder Link(s): DM3730 DM3725 261 PRODUCT PREVIEW IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. [. . . ]