User manual TEXAS INSTRUMENTS OMAP-L137 ADVANCE INFORMATION 08-2010

[. . . ] OMAP-L137 www. ti. com SPRS563D ­ SEPTEMBER 2008 ­ REVISED AUGUST 2010 OMAP-L137 Low-Power Applications Processor Check for Samples: OMAP-L137 1 OMAP-L137 Low-Power Applications Processor 1. 1 1234 Features ­ Up to 3648/2736 C674x MIPS/MFLOPS ­ Byte-Addressable (8-/16-/32-/64-Bit Data) ­ 8-Bit Overflow Protection ­ Bit-Field Extract, Set, Clear ­ Normalization, Saturation, Bit-Counting ­ Compact 16-Bit Instructions · C674x Two Level Cache Memory Architecture ­ 32K-Byte L1P Program RAM/Cache ­ 32K-Byte L1D Data RAM/Cache ­ 256K-Byte L2 Unified Mapped RAM/Cache ­ Flexible RAM/Cache Partition (L1 and L2) · Enhanced Direct-Memory-Access Controller 3 (EDMA3): ­ 2 Transfer Controllers ­ 32 Independent DMA Channels ­ 8 Quick DMA Channels ­ Programmable Transfer Burst Size · TMS320C674x Fixed/Floating-Point VLIW DSP Core ­ Load-Store Architecture With Non-Aligned Support ­ 64 General-Purpose Registers (32 Bit) ­ Six ALU (32-/40-Bit) Functional Units · Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point · Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks · Supports up to Two Floating Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle ­ Two Multiply Functional Units · Mixed-Precision IEEE Floating Point Multiply Supported up to: ­ 2 SP x SP -> SP Per Clock ­ 2 SP x SP -> DP Every Two Clocks ­ 2 SP x DP -> DP Every Three Clocks ­ 2 DP x DP -> DP Every Four Clocks · Fixed Point Multiply Supports Two 32 x · Highlights ­ Dual Core SoC · 375/456-MHz ARM926EJ-STM RISC MPU · 375/456-MHz C674x VLIW DSP ­ TMS320C674x Fixed/Floating-Point VLIW DSP Core ­ Enhanced Direct-Memory-Access Controller 3 (EDMA3) ­ 128K-Byte RAM Shared Memory ­ Two External Memory Interfaces ­ Three Configurable 16550 type UART Modules ­ LCD Controller ­ Two Serial Peripheral Interfaces (SPI) ­ Multimedia Card (MMC)/Secure Digital (SD) ­ Two Master/Slave Inter-Integrated Circuit ­ One Host-Port Interface (HPI) ­ USB 1. 1 OHCI (Host) With Integrated PHY (USB1) · Applications ­ Industrial Diagnostics ­ Test and measurement ­ Military Sonar/ Radar ­ Medical measurement ­ Professional Audio · Software Support ­ TI DSP/BIOSTM ­ Chip Support Library and DSP Library · Dual Core SoC ­ 375/456-MHz ARM926EJ-STM RISC MPU ­ 375/456-MHz C674x VLIW DSP · ARM926EJ-S Core ­ 32-Bit and 16-Bit (Thumb®) Instructions ­ DSP Instruction Extensions ­ Single Cycle MAC ­ ARM® Jazelle® Technology ­ EmbeddedICE-RTTM for Real-Time Debug · ARM9 Memory Architecture · C674x Instruction Set Features ­ Superset of the C67x+TM and C64x+TM ISAs 1 2 3 4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DSP/BIOS, C67x+, TMS320C6000, C6000 are trademarks of Texas Instruments. ARM926EJ-S, EmbeddedICE-RT, ETM9, CoreSight are trademarks of ARM Limited. ARM, Jazelle are registered trademarks of ARM Limited. Copyright © 2008­2010, Texas Instruments Incorporated ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. [. . . ] PARAMETER Cycle time, AHCLKR1 internal, AHCLKR1 output 9 tc(AHCLKRX) Cycle time, AHCLKR1 external, AHCLKR1 output Cycle time, AHCLKX1 internal, AHCLKX1 output Cycle time, AHCLKX1 external, AHCLKX1 output Pulse duration, AHCLKR1 internal, AHCLKR1 output 10 tw(AHCLKRX) Pulse duration, AHCLKR1 external, AHCLKR1 output Pulse duration, AHCLKX1 internal, AHCLKX1 output Pulse duration, AHCLKX1 external, AHCLKX1 output Cycle time, ACLKR1 internal, ACLKR1 output 11 tc(ACLKRX) Cycle time, ACLKR1 external, ACLKR1 output Cycle time, ACLKX1 internal, ACLKX1 output Cycle time, ACLKX1 external, ACLKX1 output Pulse duration, ACLKR1 internal, ACLKR1 output 12 tw(ACLKRX) Pulse duration, ACLKR1 external, ACLKR1 output Pulse duration, ACLKX1 internal, ACLKX1 output Pulse duration, ACLKX1 external, ACLKX1 output Delay time, ACLKR1 internal, AFSR output Delay time, ACLKX1 internal, AFSX output 13 td(ACLKRX-AFSRX) Delay time, ACLKR1 external input, AFSR output Delay time, ACLKX1 external input, AFSX output Delay time, ACLKR1 external output, AFSR output (7) Delay time, ACLKX1 external output, AFSX output Delay time, ACLKX1 internal, AXR1[n] output 14 td(ACLKX-AXRV) Delay time, ACLKX1 external input, AXR1[n] output Delay time, ACLKX1 external output, AXR1[n] output Disable time, ACLKX1 internal, AXR1[n] output 15 tdis(ACLKX-AXRHZ) Disable time, ACLKX1 external input, AXR1[n] output Disable time, ACLKX1 external output, AXR1[n] output (1) McASP1 ACLKX1 internal ­ ACLKXCTL. CLKXM = 1, PDIR. ACLKX = 1 McASP1 ACLKX1 external input ­ ACLKXCTL. CLKXM = 0, PDIR. ACLKX = 0 McASP1 ACLKX1 external output ­ ACLKXCTL. CLKXM = 0, PDIR. ACLKX = 1 McASP1 ACLKR1 internal ­ ACLKR1CTL. CLKRM = 1, PDIR. ACLKR =1 McASP1 ACLKR1 external input ­ ACLKRCTL. CLKRM = 0, PDIR. ACLKR = 0 McASP1 ACLKR1 external output ­ ACLKRCTL. CLKRM = 0, PDIR. ACLKR = 1 AHR - Cycle time, AHCLKR1. McASP1 ACLKXCTL. ASYNC=1: Receiver is clocked by its own ACLKR1 (7) (7) MIN 25 25 25 25 (AHR/2) ­ 2. 5 (2) (AHR/2) ­ 2. 5 (2) (AHX/2) ­ 2. 5 (3) (AHX/2) ­ 2. 5 (3) greater of 2P or 25 (4) greater of 2P or 25 (4) greater of 2P or 25 (4) greater of 2P or 25 (4) (AR/2) ­ 2. 5 (5) (AR/2) ­ 2. 5 (5) (AX/2) ­ 2. 5 (6) (AX/2) ­ 2. 5 (6) 0. 5 0. 5 3. 4 3. 4 3. 4 3. 4 0. 5 3. 4 3. 4 0. 5 3. 9 3. 9 MAX UNIT ns ns ns ns ADVANCE INFORMATION 6. 7 6. 7 13. 8 13. 8 13. 8 13. 8 6. 7 13. 8 13. 8 6. 7 13. 8 13. 8 ns ns ns (2) (3) (4) (5) (6) (7) 122 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): OMAP-L137 Copyright © 2008­2010, Texas Instruments Incorporated OMAP-L137 www. ti. com SPRS563D ­ SEPTEMBER 2008 ­ REVISED AUGUST 2010 6. 17. 2. 3 Multichannel Audio Serial Port 2 (McASP2) Timing Table 6-53 and Table 6-54 assume testing over recommended operating conditions (see Figure 6-32 and Figure 6-33). 1 2 3 4 tc(AHCLKRX) tw(AHCLKRX) tc(ACLKRX) tw(ACLKRX) Cycle time, AHCLKR2 external, AHCLKR2 input Cycle time, AHCLKX2 external, AHCLKX2 input Pulse duration, AHCLKR2 external, AHCLKR2 input Pulse duration, AHCLKX2 external, AHCLKX2 input Cycle time, ACLKR2 external, ACLKR2 input Cycle time, ACLKX2 external, ACLKX2 input Pulse duration, ACLKR2 external, ACLKR2 input Pulse duration, ACLKX2 external, ACLKX2 input Setup time, AFSR2 input to ACLKR2 internal (3) Setup time, AFSX2 input to ACLKX2 internal 5 tsu(AFSRX-ACLKRX) Setup time, AFSR2 input to ACLKR2 external input (3) Setup time, AFSX2 input to ACLKX2 external input Setup time, AFSR2 input to ACLKR2 external output (3) Setup time, AFSX2 input to ACLKX2 external output Hold time, AFSR2 input after ACLKR2 internal (3) Hold time, AFSX2 input after ACLKX2 internal 6 th(ACLKRX-AFSRX) Hold time, AFSR2 input after ACLKR2 external input (3) Hold time, AFSX2 input after ACLKX2 external input Hold time, AFSR2 input after ACLKR2 external output (3) Hold time, AFSX2 input after ACLKX2 external output Setup time, AXR2[n] input to ACLKR2 internal (3) Setup time, AXR2[n] input to ACLKX2 internal 7 tsu(AXR-ACLKRX) (4) (2) MIN 15 15 7. 5 7. 5 greater of 2P or 15 greater of 2P or 15 7. 5 7. 5 10 10 1. 6 1. 6 1. 6 -1. 7 -1. 7 1. 3 1. 3 1. 3 1. 3 10 10 1. 6 1. 6 1. 6 1. 6 -1. 7 -1. 7 (3) MAX UNIT ns ns ns ns ns ns Setup time, AXR2[n] input to ACLKR2 external input (3) Setup time, AXR2[n] input to ACLKX2 external input (4) Setup time, AXR2[n] input to ACLKR2 external output (3) Setup time, AXR2[n] input to ACLKX2 external output Hold time, AXR2[n] input after ACLKR2 internal (3) Hold time, AXR2[n] input after ACLKX2 internal (4) Hold time, AXR2[n] input after ACLKR2 external input (4) ns 8 th(ACLKRX-AXR) 1. 3 1. 3 1. 3 1. 3 Hold time, AXR2[n] input after ACLKX2 external input (4) Hold time, AXR2[n] input after ACLKR2 external output (3) Hold time, AXR2[n] input after ACLKX2 external output (4) ns (1) (2) (3) (4) ACLKX2 internal ­ McASP2 ACLKXCTL. CLKXM = 1, PDIR. ACLKX = 1 ACLKX2 external input ­ McASP2 ACLKXCTL. CLKXM = 0, PDIR. ACLKX = 0 ACLKX2 external output ­ McASP2 ACLKXCTL. CLKXM = 0, PDIR. ACLKX = 1 ACLKR2 internal ­ McASP2 ACLKRCTL. CLKRM = 1, PDIR. ACLKR =1 ACLKR2 external input ­ McASP2 ACLKRCTL. CLKRM = 0, PDIR. ACLKR = 0 ACLKR2 external output ­ McASP2 ACLKRCTL. CLKRM = 0, PDIR. ACLKR = 1 P = SYSCLK2 period McASP2 ACLKXCTL. ASYNC=1: Receiver is clocked by its own ACLKR2 McASP2 ACLKXCTL. ASYNC=0: Receiver is clocked by transmitter's ACLKX2 Copyright © 2008­2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): OMAP-L137 123 ADVANCE INFORMATION 1. 6 OMAP-L137 SPRS563D ­ SEPTEMBER 2008 ­ REVISED AUGUST 2010 www. ti. com Table 6-54. PARAMETER Cycle time, AHCLKR2 internal, AHCLKR2 output 9 tc(AHCLKRX) Cycle time, AHCLKR2 external, AHCLKR2 output Cycle time, AHCLKX2 internal, AHCLKX2 output Cycle time, AHCLKX2 external, AHCLKX2 output Pulse duration, AHCLKR2 internal, AHCLKR2 output 10 tw(AHCLKRX) Pulse duration, AHCLKR2 external, AHCLKR2 output Pulse duration, AHCLKX2 internal, AHCLKX2 output Pulse duration, AHCLKX2 external, AHCLKX2 output Cycle time, ACLKR2 internal, ACLKR2 output 11 tc(ACLKRX) Cycle time, ACLKR2 external, ACLKR2 output Cycle time, ACLKX2 internal, ACLKX2 output Cycle time, ACLKX2 external, ACLKX2 output Pulse duration, ACLKR2 internal, ACLKR2 output 12 tw(ACLKRX) Pulse duration, ACLKR2 external, ACLKR2 output Pulse duration, ACLKX2 internal, ACLKX2 output Pulse duration, ACLKX2 external, ACLKX2 output Delay time, ACLKR2 internal, AFSR output Delay time, ACLKX2 internal, AFSX output 13 td(ACLKRX-AFSRX) Delay time, ACLKR2 external input, AFSR output Delay time, ACLKX2 external input, AFSX output Delay time, ACLKR2 external output, AFSR output (7) Delay time, ACLKX2 external output, AFSX output Delay time, ACLKX2 internal, AXR2[n] output 14 td(ACLKX-AXRV) Delay time, ACLKX2 external input, AXR2[n] output Delay time, ACLKX2 external output, AXR2[n] output Disable time, ACLKX2 internal, AXR2[n] output 15 tdis(ACLKX-AXRHZ) Disable time, ACLKX2 external input, AXR2[n] output Disable time, ACLKX2 external output, AXR2[n] output (1) McASP2 ACLKX2 internal ­ ACLKXCTL. CLKXM = 1, PDIR. ACLKX = 1 McASP2 ACLKX2 external input ­ ACLKXCTL. CLKXM = 0, PDIR. ACLKX = 0 McASP2 ACLKX2 external output ­ ACLKXCTL. CLKXM = 0, PDIR. ACLKX = 1 McASP2 ACLKR2 internal ­ ACLKR2CTL. CLKRM = 1, PDIR. ACLKR =1 McASP2 ACLKR2 external input ­ ACLKRCTL. CLKRM = 0, PDIR. ACLKR = 0 McASP2 ACLKR2 external output ­ ACLKRCTL. CLKRM = 0, PDIR. ACLKR = 1 AHR - Cycle time, AHCLKR2. McASP2 ACLKXCTL. ASYNC=1: Receiver is clocked by its own ACLKR2 (7) (7) MIN 15 15 15 15 (AHR/2) ­ 2. 5 (2) (AHR/2) ­ 2. 5 (2) (AHX/2) ­ 2. 5 (3) (AHX/2) ­ 2. 5 (3) greater of 2P or 15 (4) greater of 2P or 15 (4) greater of 2P or 15 (4) greater of 2P or 15 (4) (AR/2) ­ 2. 5 (5) (AR/2) ­ 2. 5 (5) (AX/2) ­ 2. 5 (6) (AX/2) ­ 2. 5 (6) -1. 4 -1. 4 2. 1 2. 1 2. 1 2. 1 -1. 4 2. 1 2. 1 -1. 4 2. 9 2. 9 MAX UNIT ns ns ns ns ADVANCE INFORMATION 2. 8 2. 8 10 10 10 10 2. 8 10 10 2. 8 10 10 ns ns ns (2) (3) (4) (5) (6) (7) 124 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): OMAP-L137 Copyright © 2008­2010, Texas Instruments Incorporated OMAP-L137 www. ti. com SPRS563D ­ SEPTEMBER 2008 ­ REVISED AUGUST 2010 2 1 AHCLKR/X (Falling Edge Polarity) AHCLKR/X (Rising Edge Polarity) 4 3 ACLKR/X (CLKRP = CLKXP = 0)(A) ACLKR/X (CLKRP = CLKXP = 1)(B) 6 5 AFSR/X (Bit Width, 0 Bit Delay) AFSR/X (Bit Width, 1 Bit Delay) AFSR/X (Bit Width, 2 Bit Delay) AFSR/X (Slot Width, 0 Bit Delay) AFSR/X (Slot Width, 1 Bit Delay) AFSR/X (Slot Width, 2 Bit Delay) 8 7 AXR[n] (Data In/Receive) A0 A1 A30 A31 B0 B1 B30 B31 C0 C1 C2 C3 C31 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP falling edge (to shift data in). 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP rising edge (to shift data in). B. For CLKRP = CLKXP = receiver is configured for For CLKRP = CLKXP = receiver is configured for Figure 6-32. McASP Input Timings Copyright © 2008­2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): OMAP-L137 125 ADVANCE INFORMATION OMAP-L137 SPRS563D ­ SEPTEMBER 2008 ­ REVISED AUGUST 2010 www. ti. com 10 9 AHCLKR/X (Falling Edge Polarity) AHCLKR/X (Rising Edge Polarity) 12 12 10 11 ACLKR/X (CLKRP = CLKXP = 1)(A) ACLKR/X (CLKRP = CLKXP = 0)(B) 13 13 AFSR/X (Bit Width, 0 Bit Delay) 13 13 ADVANCE INFORMATION 126 AFSR/X (Bit Width, 1 Bit Delay) AFSR/X (Bit Width, 2 Bit Delay) 13 AFSR/X (Slot Width, 0 Bit Delay) 13 13 AFSR/X (Slot Width, 1 Bit Delay) AFSR/X (Slot Width, 2 Bit Delay) 14 15 AXR[n] (Data Out/Transmit) A0 A. For CLKRP = CLKXP = receiver is configured for For CLKRP = CLKXP = receiver is configured for A1 A30 A31 B0 B1 B30 B31 C0 C1 C2 C3 C31 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP rising edge (to shift data in). 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP falling edge (to shift data in). Figure 6-33. McASP Output Timings Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): OMAP-L137 Copyright © 2008­2010, Texas Instruments Incorporated OMAP-L137 www. ti. com SPRS563D ­ SEPTEMBER 2008 ­ REVISED AUGUST 2010 6. 18 Serial Peripheral Interface Ports (SPI0, SPI1) Figure 6-34 is a block diagram of the SPI module, which is a simple shift register and buffer plus control logic. Data is written to the shift register before transmission occurs and is read from the buffer at the end of transmission. The SPI can operate either as a master, in which case, it initiates a transfer and drives the SPIx_CLK pin, or as a slave. Four clock phase and polarity options are supported as well as many data formatting options. SPIx_SIMO SPIx_SOMI Peripheral Configuration Bus 16-Bit Shift Register GPIO Control (all pins) State Machine Clock Control SPIx_ENA SPIx_SCS SPIx_CLK Interrupt and DMA Requests 16-Bit Buffer The SPI supports 3-, 4-, and 5-pin operation with three basic pins (SPIx_CLK, SPIx_SIMO, and SPIx_SOMI) and two optional pins (SPIx_SCS, SPIx_ENA). The optional SPIx_SCS (Slave Chip Select) pin is most useful to enable in slave mode when there are other slave devices on the same SPI port. The OMAP-L137 will only shift data and drive the SPIx_SOMI pin when SPIx_SCS is held low. The SPIx_ENA output provides the status of the internal transmit buffer (SPIDAT0/1 registers). In four-pin mode with the enable option, SPIx_ENA is asserted only when the transmit buffer is full, indicating that the slave is ready to begin another transfer. In five-pin mode, the SPIx_ENA is additionally qualified by SPIx_SCS being asserted. This allows a single handshake line to be shared by multiple slaves on the same SPI bus. In master mode, the SPIx_ENA pin is an optional input and the master can be configured to delay the start of the next transfer until the slave asserts SPIx_ENA. The addition of this handshake signal simplifies SPI communications and, on average, increases SPI bus throughput since the master does not need to delay each transfer long enough to allow for the worst-case latency of the slave device. [. . . ] In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. [. . . ]