User manual TEXAS INSTRUMENTS OMAP-L138 ADVANCE INFORMATION 08-2010

[. . . ] OMAP-L138 www. ti. com SPRS586B ­ JUNE 2009 ­ REVISED AUGUST 2010 OMAP-L138 Low-Power Applications Processor Check for Samples: OMAP-L138 1 OMAP-L138 Low-Power Applications Processor 1. 1 123 Features ­ Normalization, Saturation, Bit-Counting ­ Compact 16-Bit Instructions · C674x Two Level Cache Memory Architecture ­ 32K-Byte L1P Program RAM/Cache ­ 32K-Byte L1D Data RAM/Cache ­ 256K -Byte L2 Unified Mapped RAM/Cache ­ Flexible RAM/Cache Partition (L1 and L2) · Enhanced Direct-Memory-Access Controller 3 (EDMA3): ­ 2 Channel Controllers ­ 3 Transfer Controllers ­ 64 Independent DMA Channels ­ 16 Quick DMA Channels ­ Programmable Transfer Burst Size · TMS320C674x Floating-Point VLIW DSP Core ­ Load-Store Architecture With Non-Aligned Support ­ 64 General-Purpose Registers (32 Bit) ­ Six ALU (32-/40-Bit) Functional Units · Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point · Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks · Supports up to Two Floating Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle ­ Two Multiply Functional Units · Mixed-Precision IEEE Floating Point Multiply Supported up to: ­ 2 SP x SP -> SP Per Clock ­ 2 SP x SP -> DP Every Two Clocks ­ 2 SP x DP -> DP Every Three Clocks ­ 2 DP x DP -> DP Every Four Clocks · Fixed Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples ­ Instruction Packing Reduces Code Size ­ All Instructions Conditional · Highlights ­ Dual Core SoC · 375/456-MHz ARM926EJ-STM RISC MPU · 375/456-MHz C674x Fixed/Floating-Point VLIW DSP ­ Enhanced Direct-Memory-Access Controller (EDMA3) ­ Serial ATA (SATA) Controller ­ DDR2/Mobile DDR Memory Controller ­ Two Multimedia Card (MMC)/Secure Digital (SD) Card Interface ­ LCD Controller ­ Video Port Interface (VPIF) ­ 10/100 Mb/s Ethernet MAC (EMAC): ­ Programmable Real-Time Unit Subsystem ­ Three Configurable UART Modules ­ USB 1. 1 OHCI (Host) With Integrated PHY ­ USB 2. 0 OTG Port With Integrated PHY ­ One Multichannel Audio Serial Port ­ Two Multichannel Buffered Serial Ports · Dual Core SoC ­ 375/456-MHz ARM926EJ-STM RISC MPU ­ 375/456-MHz C674x VLIW DSP · ARM926EJ-S Core ­ 32-Bit and 16-Bit (Thumb®) Instructions ­ DSP Instruction Extensions ­ Single Cycle MAC ­ ARM® Jazelle® Technology ­ EmbeddedICE-RTTM for Real-Time Debug · ARM9 Memory Architecture ­ 16K-Byte Instruction Cache ­ 16K-Byte Data Cache ­ 8K-Byte RAM (Vector Table) ­ 64K-Byte ROM · C674x Instruction Set Features ­ Superset of the C67x+TM and C64x+TM ISAs ­ Up to 3648/2746 C674x MIPS/MFLOPS ­ Byte-Addressable (8-/16-/32-/64-Bit Data) ­ 8-Bit Overflow Protection ­ Bit-Field Extract, Set, Clear 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. ARM926EJ-S is a trademark of ARM Limited. Copyright © 2009­2010, Texas Instruments Incorporated ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. ADVANCE INFORMATION OMAP-L138 SPRS586B ­ JUNE 2009 ­ REVISED AUGUST 2010 www. ti. com · · · · · · · · · · · ­ Hardware Support for Modulo Loop Operation ­ Protected Mode Operation ­ Exceptions Support for Error Detection and Program Redirection Software Support ­ TI DSP/BIOSTM ­ Chip Support Library and DSP Library 128K-Byte RAM Shared Memory 1. 8V or 3. 3V LVCMOS IOs (except for USB and DDR2 interfaces) Two External Memory Interfaces: ­ EMIFA · NOR (8-/16-Bit-Wide Data) · NAND (8-/16-Bit-Wide Data) · 16-Bit SDRAM With 128 MB Address Space ­ DDR2/Mobile DDR Memory Controller · 16-Bit DDR2 SDRAM With 512 MB Address Space or · 16-Bit mDDR SDRAM With 256 MB Address Space Three Configurable 16550 type UART Modules: ­ With Modem Control Signals ­ 16-byte FIFO ­ 16x or 13x Oversampling Option LCD Controller Two Serial Peripheral Interfaces (SPI) Each With Multiple Chip-Selects Two Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO) Interfaces Two Master/Slave Inter-Integrated Circuit (I2C BusTM) One Host-Port Interface (HPI) With 16-Bit-Wide Muxed Address/Data Bus For High Bandwidth Programmable Real-Time Unit Subsystem (PRUSS) ­ Two Independent Programmable Realtime Unit (PRU) Cores · 32-Bit Load/Store RISC architecture · 4K Byte instruction RAM per core · 512 Bytes data RAM per core · PRU Subsystem (PRUSS) can be disabled via software to save power · Register 30 of each PRU is exported from the subsystem in addition to the normal R31 output of the PRU cores. ­ Standard power management mechanism · Clock gating · Entire subsystem under a single PSC clock gating domain ­ Dedicated interrupt controller ­ Dedicated switched central resource · USB 1. 1 OHCI (Host) With Integrated PHY (USB1) · USB 2. 0 OTG Port With Integrated PHY (USB0) ­ USB 2. 0 High-/Full-Speed Client ­ USB 2. 0 High-/Full-/Low-Speed Host ­ End Point 0 (Control) ­ End Points 1, 2, 3, 4 (Control, Bulk, Interrupt or ISOC) Rx and Tx · One Multichannel Audio Serial Port: ­ Two Clock Zones and 16 Serial Data Pins ­ Supports TDM, I2S, and Similar Formats ­ DIT-Capable ­ FIFO buffers for Transmit and Receive · Two Multichannel Buffered Serial Ports: ­ Supports TDM, I2S, and Similar Formats ­ AC97 Audio Codec Interface ­ Telecom Interfaces (ST-Bus, H100) ­ 128-channel TDM ­ FIFO buffers for Transmit and Receive · 10/100 Mb/s Ethernet MAC (EMAC): ­ IEEE 802. 3 Compliant ­ MII Media Independent Interface ­ RMII Reduced Media Independent Interface ­ Management Data I/O (MDIO) Module · Video Port Interface (VPIF): ­ Two 8-bit SD (BT. 656), Single 16-bit or Single Raw (8-/10-/12-bit) Video Capture Channels ­ Two 8-bit SD (BT. 656), Single 16-bit Video Display Channels · Universal Parallel Port (uPP): ­ High-Speed Parallel Interface to FPGAs and Data Converters ­ Data Width on Each of Two Channels is 8- to 16-bit Inclusive ­ Single Data Rate or Dual Data Rate Transfers ­ Supports Multiple Interfaces with START, ENABLE and WAIT Controls · Serial ATA (SATA) Controller: ­ Supports SATA I (1. 5 Gbps) and SATA II (3. 0 Gbps) ­ Supports all SATA Power Management Features ­ Hardware-Assisted Native Command Queueing (NCQ) for up to 32 Entries ­ Supports Port Multiplier and Command-Based Switching · Real-Time Clock With 32 KHz Oscillator and Separate Power Rail · Three 64-Bit General-Purpose Timers (Each configurable as Two 32-Bit Timers) · One 64-bit General-Purpose/Watchdog Timer (Configurable as Two 32-bit General-Purpose Timers) Copyright © 2009­2010, Texas Instruments Incorporated ADVANCE INFORMATION 2 OMAP-L138 Low-Power Applications Processor Submit Documentation Feedback Product Folder Link(s): OMAP-L138 OMAP-L138 www. ti. com SPRS586B ­ JUNE 2009 ­ REVISED AUGUST 2010 · Two Enhanced Pulse Width Modulators (eHRPWM): ­ Dedicated 16-Bit Time-Base Counter With Period And Frequency Control ­ 6 Single Edge, 6 Dual Edge Symmetric or 3 Dual Edge Asymmetric Outputs ­ Dead-Band Generation ­ PWM Chopping by High-Frequency Carrier ­ Trip Zone Input · Three 32-Bit Enhanced Capture Modules (eCAP): ­ Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) · · · · outputs ­ Single Shot Capture of up to Four Event Time-Stamps 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZCE Suffix], 0. 65-mm Ball Pitch 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZWT Suffix], 0. 80-mm Ball Pitch Commercial, Extended or Industrial Temperature Community Resources ­ TI E2E Community ­ TI Embedded Processors Wiki Copyright © 2009­2010, Texas Instruments Incorporated OMAP-L138 Low-Power Applications Processor Submit Documentation Feedback Product Folder Link(s): OMAP-L138 3 ADVANCE INFORMATION OMAP-L138 SPRS586B ­ JUNE 2009 ­ REVISED AUGUST 2010 www. ti. com 1. 2 Trademarks DSP/BIOS, TMS320C6000, C6000, TMS320, TMS320C62x, and TMS320C67x are trademarks of Texas Instruments. [. . . ] VREF is intended to be half the DDR2/mDDR power supply voltage and should be created using a resistive divider as shown in Figure 6-18. Figure 6-22 shows the layout guidelines for VREF. VREF Bypass Capacitor DDR2/mDDR Device A1 VREF Nominal Minimum Trace Width is 20 Mils DDR2/mDDR A1 Neck down to minimum in BGA escape regions is acceptable. Narrowing to accomodate via congestion for short distances is also acceptable. Best performance is obtained if the width of VREF is maximized. ADVANCE INFORMATION 138 Figure 6-22. VREF Routing and Topology Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): OMAP-L138 Copyright © 2009­2010, Texas Instruments Incorporated OMAP-L138 www. ti. com SPRS586B ­ JUNE 2009 ­ REVISED AUGUST 2010 6. 11. 3. 11 DDR2/mDDR CK and ADDR_CTRL Routing Figure 6-23 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A should be maximized. A1 T A C A1 Figure 6-23. 1 2 3 4 5 6 7 8 9 10 11 Parameter Center to Center CK-CKN Spacing CK A to B/A to C Skew Length Mismatch CK B to C Skew Length Mismatch Center to center CK to other DDR2/mDDR trace spacing CK/ADDR_CTRL nominal trace length ADDR_CTRL to CK Skew Length Mismatch ADDR_CTRL to ADDR_CTRL Skew Length Mismatch Center to center ADDR_CTRL to other DDR2/mDDR trace spacing Center to center ADDR_CTRL to other ADDR_CTRL trace spacing ADDR_CTRL A to B/A to C Skew Length Mismatch ADDR_CTRL B to C Skew Length Mismatch 4w 3w (1) (1) (1) DDR2/mDDR Controller B Min Typ Max 2w (1) Unit Notes (2) 25 25 4w Mils Mils See Note See Note CACLM CACLM+50 100 100 Mils Mils Mils See Note See Note 100 100 Mils Mils See Note See Note (3) (4) CACLM-50 (3) (3) (2) (1) (2) (3) (4) w = PCB trace width as defined in Table 6-29. Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion. CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes. Copyright © 2009­2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): OMAP-L138 139 ADVANCE INFORMATION OMAP-L138 SPRS586B ­ JUNE 2009 ­ REVISED AUGUST 2010 www. ti. com Figure 6-24 shows the topology and routing for the DQS and D net class; the routes are point to point. Skew matching across bytes is not needed nor recommended. T A1 T A1 E1 Figure 6-24. 2 Parameter Center to center DQS to other DDR2/mDDR trace spacing DQS/D nominal trace length D to DQS Skew Length Mismatch D to D Skew Length Mismatch Center to center D to other DDR2/mDDR trace spacing Center to Center D to other D trace spacing 4w 3w (1) Min 4w (1) DDR2/mDDR Controller E0 Typ Max Unit Notes See Note (2) ADVANCE INFORMATION 3 4 5 6 7 (1) (2) (3) (4) (5) (6) DQLM-50 DQLM DQLM+50 100 100 Mils Mils Mils See Notes See Note See Note (3) (4) , (4) (4) (2) (5) See Notes See Notes , (1) (6) (2) , w = PCB trace width as defined in Table 6-29 Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion. There is no need and it is not recommended to skew match across data bytes, i. e. , from DQS0 and data byte 0 to DQS1 and data byte 1. DQLM is the longest Manhattan distance of each of the DQS and D net class. 140 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): OMAP-L138 Copyright © 2009­2010, Texas Instruments Incorporated OMAP-L138 www. ti. com SPRS586B ­ JUNE 2009 ­ REVISED AUGUST 2010 Figure 6-25 shows the routing for the DQGATE net class. Table 6-38 contains the routing specification. A1 T A1 Figure 6-25. 1 2 3 4 (1) (2) (3) Parameter DQGATE Length F Center to center DQGATE to any other trace spacing DQS/D nominal trace length DQGATE Skew CKB0B1 is the sum of the length of the CK net plus the average length of the DQS0 and DQS1 nets. w = PCB trace width as defined in Table 6-29 Skew from CKB0B1 4w (2) DDR2/mDDR Controller F T Min Typ CKB0B1 Max Unit Notes See Note (1) DQLM-50 DQLM DQLM+50 100 Mils Mils See Note (3) 6. 11. 3. 12 MDDR/DDR2 Boundary Scan Limitations Due to DDR implementation and timing restrictions, it was not possible to place boundary scan cells between core logic and the IO like boundary scan cells for other IO. Instead, the boundary scan cells are tapped-off to the DDR PHY and there is the equivalent of a multiplexer inside the DDR PHY which selects between functional and boundary scan paths. The implication for boundary scan is that the DDR pins will not support the SAMPLE function of the output enable cells on the DDR pins and this is a violation of IEEE 1149. 1. Full EXTEST and PRELOAD capability is still available. Copyright © 2009­2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): OMAP-L138 141 ADVANCE INFORMATION OMAP-L138 SPRS586B ­ JUNE 2009 ­ REVISED AUGUST 2010 www. ti. com 6. 12 Memory Protection Units The MPU performs memory protection checking. It receives requests from a bus master in the system and checks the address against the fixed and programmable regions to see if the access is allowed. If allowed, the transfer is passed unmodified to its output bus (to the targeted address). [. . . ] In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. [. . . ]