User manual TEXAS INSTRUMENTS SM320C6472 FIXED-POINT DIGITAL SIGNAL PROCESSOR FEATURES 10-2010

[. . . ] SM320C6472-HiRel www. ti. com SPRS696B ­ SEPTEMBER 2010 ­ REVISED OCTOBER 2010 SM320C6472 Fixed-Point Digital Signal Processor 1 Features 1 · Six On-Chip TMS320C64x+ Megamodules · Endianess: Little Endian, Big Endian · C64x+ Megamodule Main Features: ­ High-Performance, Fixed-Point TMS320C64x+ DSP ­ 500/625/700 MHz ­ Eight 32-Bit Instructions/Cycle ­ 4000 MIPS/MMACS (16-Bits) at 500 MHz ­ Dedicated SPLOOP Instruction ­ Compact Instructions (16-Bit) ­ Instruction Set Enhancements ­ Exception Handling ­ L1/L2 Memory Architecture: · 256K-Bit (32K-Byte) L1P Program RAM/Cache [Direct Mapped, Flexible Allocation] · 256K-Bit (32K-Byte) L1D RAM/Cache [2-Way Set-Associative, Flexible Allocation] · 4. 75M-Bit (608K-Byte) L2 Unified Mapped RAM/Cache [4-Way Set-Associative, Flexible Allocation] · L1P Memory Controller · L1D Memory Controller · L2 Memory Controller ­ Time Stamp Counter ­ One 64-Bit General-Purpose/Watchdog Timer · Shared Peripherals and Interfaces ­ EDMA Controller (64 Independent Channels) ­ Shared Memory Architecture · Shared L2 Memory Controller · 768K-Byte of RAM · Boot ROM ­ Three Telecom Serial Interface Ports (TSIPs) · Each TSIP is 8 Links of 8 Mbps per Direction ­ 32-Bit DDR2 Memory Controller (DDR2-533 SDRAM) · 256 M-Byte x 2 Addressable Memory Space ­ Two 1x Serial RapidIO® Links, v1. 2 Compliant · 1. 25-, 2. 5-, 3. 125-Gbps Link Rates · Message Passing, DirectIO Support, Error Management Extensions, and 1 · · · · · · · · · · · · Congestion Control · IEEE 1149. 6 Compliant I/Os ­ UTOPIA · UTOPIA Level 2 Slave ATM Controller · 8/16-Bit Transmit and Receive Operations up to 50 MHz per Direction · User-Defined Cell Format up to 64 Bytes ­ Two 10/100/1000 Mb/s Ethernet MACs (EMACs) · Both EMACs are IEEE 802. 3 Compliant · EMAC0 Supports: ­ MII, RMII, SS-SMII, GMII, and RGMII ­ 8 Independent Transmit (TX) Channels ­ 8 Independent Receive (RX) Channels · EMAC1 Supports: ­ RMII, SS-SMII and RGMII ­ 8 Independent Transmit (TX) Channels ­ 8 Independent Receive (RX) Channels · Both EMACs (EMAC0 and EMAC1) Share MDIO Interface ­ 16-Bit Host-Port Interface (HPI) ­ One Inter-Integrated Circuit (I2C) Bus ­ Six Shared 64-Bit General-Purpose Timers System PLL and PLL Controller Secondary PLL and PLL Controller, Dedicated to EMAC Third PLL and PLL Controller Dedicated to DDR2 Memory Controller 16 General-Purpose I/O (GPIO) Pins IEEE-1149. 1 (JTAGTM) Boundary-Scan-Compatible 737-Pin Ball Grid Array (BGA) Package (ZTZ/GTZ Suffix), 0. 8-mm Ball Pitch 0. 09-mm/7-Level Cu Metal Process (CMOS) 3. 3-, 1. 8-, 1. 5-, 1. 2-V I/O Supplies 1. 0-/1. 1-, 1. 2-V Core Supplies Commercial Temperature [0°C to 85°C] Extended Temperature [-40°C to 100°C] Only 625-MHz Device Offered in GTZ Package Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright © 2010, Texas Instruments Incorporated PRODUCT PREVIEW SM320C6472-HiRel SPRS696B ­ SEPTEMBER 2010 ­ REVISED OCTOBER 2010 www. ti. com 1. 1 ZTZ/GTZ BGA Package (Bottom View) The SM320C6472 devices are designed for a package temperature range of 0°C to 85°C (commercial temperature range) or -40°C to 100°C (extended temperature range). NOTE Extended temperature (A) range is available only on 500-MHz and 625-MHz devices. AJ AH AF AD AG AE AC AB AA Y W V U T R P N M L K J H G F E D C B A PRODUCT PREVIEW 2 Features 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 2 4 6 8 10 12 14 16 18 20 22 24 26 28 Figure 1-1. ZTZ/GTZ 737-Pin Ball Grid Array (BGA) Package (Bottom View) Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) :SM320C6472-HiRel SM320C6472-HiRel www. ti. com SPRS696B ­ SEPTEMBER 2010 ­ REVISED OCTOBER 2010 1. 2 Description The SM320C6472 device is a Texas Instruments next-generation fixed-point digital signal processor (DSP) targeting high-performance computing applications, including high-end industrial, mission-critical, high-end image and video, communication, media gateways, and remote access servers. [. . . ] A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timings. Input requirements in this data sheet are tested with an input slew rate of 4 Volts per nanosecond (V/ns) at the device pin. Figure 7-1. Test Load Circuit for AC Timing Measurements The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving. 7. 1. 1 3. 3-V Signal Transition Levels All input and output timing parameters are referenced to 1. 5 V for both "0" and "1" logic levels. Vref = 1. 5 V Figure 7-2. Input and Output Voltage Reference Levels for AC Timing Measurements All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOLMAX and VOH MIN for output clocks. Vref = VIH MIN (or VOH MIN) Vref = VIL MAX (or VOL MAX) Figure 7-3. Rise and Fall Transition Time Voltage Reference Levels 7. 1. 2 3. 3-V Signal Transition Rates All timings are tested with an input edge rate of 4 Volts per nanosecond (V/ns). 7. 1. 3 Timing Parameters and Board Routing Analysis The timing parameter values specified in this data sheet do not include delays by board routings. As a good board design practice, such delays must always be taken into account. Timing values may be Copyright © 2010, Texas Instruments Incorporated C64x+ Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s) :SM320C6472-HiRel 115 PRODUCT PREVIEW SM320C6472-HiRel SPRS696B ­ SEPTEMBER 2010 ­ REVISED OCTOBER 2010 www. ti. com adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing differences. 7. 2 Recommended Clock and Control Signal Transition Behavior All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic manner. 7. 3 7. 3. 1 Power Supplies Power-Supply Sequencing TI recommends the power-supply sequence options shown in Figure 7-4 and Figure 7-5. For Option 2, after the DVDD33 supply is stable, the remaining power supplies can be powered up at the same time as CVDD as long as their supply voltage never exceeds the CVDD voltage until CVDD is stable. Note that the word stable means voltages that have reached a valid level as described in Section 6. 2. Some TI power-supply devices include an "auto-track" feature that can be used to ensure multiple supply outputs ramp at the same time to prevent one being higher than another during startup. In all of these sequencing requirements, the intent is to prevent a subsequent power supply voltage from exceeding a previous power supply until the previous supply has reached a stable value. DVDD33 CVDD CVDD1 CVDD2 PRODUCT PREVIEW 1 2 DVDD18 and other 1. 8-V supplies VREFSSSTL (DDR2) DVDD15 and other 1. 5-V supplies VREFHSTL (RGMII) 1. 2-V SERDES supplies 4 3 Figure 7-4. Power-Supply Sequence (Option 1) DVDD33 CVDD All other power supplies 1 2 Figure 7-5. Power-Supply Sequence (Option 2) 116 C64x+ Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s) :SM320C6472-HiRel Copyright © 2010, Texas Instruments Incorporated SM320C6472-HiRel www. ti. com SPRS696B ­ SEPTEMBER 2010 ­ REVISED OCTOBER 2010 Table 7-1. 1 2 3 4 (1) tsu(DVDD33-CVDD) tsu(CVDD-DVDD18) tsu(DVDD18-DVDD15) tsu(DVDD15-DVDD) Setup time, DVDD33 supply stable before CVDD supply stable Setup time, CVDD supply stable before DVDD18 supply and VREFSSTL reference voltage stable Setup time, DVDD18 supply and VREFSSTL reference voltage stable before DVDD15 supply and VREFHSTL reference voltage stable Setup time, DVDD15 supply and VREFHSTL reference voltage stable before DVDD supply stable 500/625/700 MIN 0. 5 0 0 0 MAX 200 200 200 200 UNIT ms ms ms ms Note: The word stable means voltages that have reached a valid level as described in Section 6. 2. Table 7-2. 1 2 (1) tsu(DVDD33-CVDD) tsu(CVDD-ALLSUP) Setup time, DVDD33 supply stable before CVDD supply stable Setup time, CVDD supply stable before all other supplies stable 500/625/700 MIN 0. 5 0 MAX 200 200 UNIT ms ms Note: The word stable means voltages that have reached a valid level as described in Section 6. 2. 7. 3. 2 Power-Supply Decoupling In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as possible close to the DSP. These caps need to be close to the DSP, no more than 1. 25 cm maximum distance to be effective. Physically smaller caps are better, such as 0402, but need to be evaluated from a yield/manufacturing point-of-view. [. . . ] In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. [. . . ]