User manual TEXAS INSTRUMENTS SM320F28335-HT DATA MANUAL

[. . . ] SM320F28335-HT Digital Signal Controller (DSC) Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Literature Number: SPRS682 December 2010 SM320F28335-HT SPRS682 ­ DECEMBER 2010 www. ti. com Contents 1 2 3 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [. . . ] CPU-Timers The timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in Figure 4-3. INT1 to INT12 PIE TINT0 CPU-TIMER 0 28x CPU TINT1 INT13 XINT13 INT14 TINT2 CPU-TIMER 2 (Reserved for DSP/BIOS) CPU-TIMER 1 A. B. The timer registers are connected to the memory bus of the C28x processor. The timing of the timers is synchronized to SYSCLKOUT of the processor clock. Figure 4-3. CPU-Timer Interrupt Signals and Output Signal The general operation of the timer is as follows: The 32-bit counter register "TIMH:TIM" is loaded with the value in the period register "PRDH:PRD". When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The registers listed in Table 4-1 are used to configure the timers. Copyright © 2010, Texas Instruments Incorporated Peripherals Submit Documentation Feedback Product Folder Link(s): SM320F28335-HT 53 SM320F28335-HT SPRS682 ­ DECEMBER 2010 www. ti. com Table 4-1. CPU-Timers 0, 1, 2 Configuration and Control Registers NAME TIMER0TIM TIMER0TIMH TIMER0PRD TIMER0PRDH TIMER0TCR Reserved TIMER0TPR TIMER0TPRH TIMER1TIM TIMER1TIMH TIMER1PRD TIMER1PRDH TIMER1TCR Reserved TIMER1TPR TIMER1TPRH TIMER2TIM TIMER2TIMH TIMER2PRD TIMER2PRDH TIMER2TCR Reserved TIMER2TPR TIMER2TPRH Reserved ADDRESS 0x0C00 0x0C01 0x0C02 0x0C03 0x0C04 0x0C05 0x0C06 0x0C07 0x0C08 0x0C09 0x0C0A 0x0C0B 0x0C0C 0x0C0D 0x0C0E 0x0C0F 0x0C10 0x0C11 0x0C12 0x0C13 0x0C14 0x0C15 0x0C16 0x0C17 0x0C18 0x0C3F SIZE (x16) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 40 CPU-Timer 2, Prescale Register CPU-Timer 2, Prescale Register High CPU-Timer 1, Prescale Register CPU-Timer 1, Prescale Register High CPU-Timer 2, Counter Register CPU-Timer 2, Counter Register High CPU-Timer 2, Period Register CPU-Timer 2, Period Register High CPU-Timer 2, Control Register CPU-Timer 0, Prescale Register CPU-Timer 0, Prescale Register High CPU-Timer 1, Counter Register CPU-Timer 1, Counter Register High CPU-Timer 1, Period Register CPU-Timer 1, Period Register High CPU-Timer 1, Control Register CPU-Timer 0, Counter Register CPU-Timer 0, Counter Register High CPU-Timer 0, Period Register CPU-Timer 0, Period Register High CPU-Timer 0, Control Register DESCRIPTION 54 Peripherals Submit Documentation Feedback Product Folder Link(s): SM320F28335-HT Copyright © 2010, Texas Instruments Incorporated SM320F28335-HT www. ti. com SPRS682 ­ DECEMBER 2010 4. 3 Enhanced PWM Modules (ePWM1/2/3/4/5/6) The F28335 contains up to six enhanced PWM Modules (ePWM). Table 4-2 shows the complete ePWM register set per module and Table 4-3 shows the remapped register configuration. EPWM1SYNCI EPWM1INT EPWM1SOC EPWM1SYNCI EPWM1A ePWM1 module EPWM1B TZ1 to TZ6 EPWM1SYNCO to eCAP1 and ePWM4 module (sync in) EPWM2INT PIE EPWM2SOC . EPWM1SYNCO EPWM2SYNCI EPWM2A ePWM2 module EPWM2B TZ1 to TZ6 GPIO MUX EPWM2SYNCO EPWMxSYNCI EPWMxINT EPWMxSOC ePWMx module EPWMxA EPWMxB TZ1 to TZ6 ADCSOCxO Peripheral Bus (A) EPWMxSYNCO ADC A. B. ADCSOCxO is sent to the DMA as well when the ePWM registers are remapped to PF3 (through bit 0 of the MAPCNF register). By default, ePWM/HRPWM registers are mapped to Peripheral Frame 1 (PF1). To re-map the registers to Peripheral Frame 3 (PF3) to enable DMA access, bit 0 (MAPEPWM) of MAPCNF register (address 0x702E) must be set to 1. Multiple PWM Modules Copyright © 2010, Texas Instruments Incorporated Peripherals Submit Documentation Feedback Product Folder Link(s): SM320F28335-HT 55 SM320F28335-HT SPRS682 ­ DECEMBER 2010 www. ti. com Table 4-2. ePWM Control and Status Registers (default configuration in PF1) NAME TBCTL TBSTS TBPHSHR TBPHS TBCTR TBPRD CMPCTL CMPAHR CMPA CMPB AQCTLA AQCTLB AQSFRC AQCSFRC DBCTL DBRED DBFED TZSEL TZCTL TZEINT TZFLG TZCLR TZFRC ETSEL ETPS ETFLG ETCLR ETFRC PCCTL HRCNFG (1) EPWM1 0x6800 0x6801 0x6802 0x6803 0x6804 0x6805 0x6807 0x6808 0x6809 0x680A 0x680B 0x680C 0x680D 0x680E 0x680F 0x6810 0x6811 0x6812 0x6814 0x6815 0x6816 0x6817 0x6818 0x6819 0x681A 0x681B 0x681C 0x681D 0x681E 0x6820 EPWM2 0x6840 0x6841 0x6842 0x6843 0x6844 0x6845 0x6847 0x6848 0x6849 0x684A 0x684B 0x684C 0x684D 0x684E 0x684F 0x6850 0x6851 0x6852 0x6854 0x6855 0x6856 0x6857 0x6858 0x6859 0x685A 0x685B 0x685C 0x685D 0x685E 0x6860 EPWM3 0x6880 0x6881 0x6882 0x6883 0x6884 0x6885 0x6887 0x6888 0x6889 0x688A 0x688B 0x688C 0x688D 0x688E 0x688F 0x6890 0x6891 0x6892 0x6894 0x6895 0x6896 0x6897 0x6898 0x6899 0x689A 0x689B 0x689C 0x689D 0x689E 0x68A0 EPWM4 0x68C0 0x68C1 0x68C2 0x68C3 0x68C4 0x68C5 0x68C7 0x68C8 0x68C9 0x68CA 0x68CB 0x68CC 0x68CD 0x68CE 0x68CF 0x68D0 0x68D1 0x68D2 0x68D4 0x68D5 0x68D6 0x68D7 0x68D8 0x68D9 0x68DA 0x68DB 0x68DC 0x68DD 0x68DE 0x68E0 EPWM5 0x6900 0x6901 0x6902 0x6903 0x6904 0x6905 0x6907 0x6908 0x6909 0x690A 0x690B 0x690C 0x690D 0x690E 0x690F 0x6910 0x6911 0x6912 0x6914 0x6915 0x6916 0x6917 0x6918 0x6919 0x691A 0x691B 0x691C 0x691D 0x691E 0x6920 EPWM6 0x6940 0x6941 0x6942 0x6943 0x6944 0x6945 0x6947 0x6948 0x6949 0x694A 0x694B 0x694C 0x694D 0x694E 0x694F 0x6950 0x6951 0x6952 0x6954 0x6955 0x6956 0x6957 0x6958 0x6959 0x695A 0x695B 0x695C 0x695D 0x695E 0x6960 SIZE (x16) / #SHADOW 1/0 1/0 1/0 1/0 1/0 1/1 1/0 1/1 1/1 1/1 1/0 1/0 1/0 1/1 1/1 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 DESCRIPTION Time Base Control Register Time Base Status Register Time Base Phase HRPWM Register Time Base Phase Register Time Base Counter Register Time Base Period Register Set Counter Compare Control Register Time Base Compare A HRPWM Register Counter Compare A Register Set Counter Compare B Register Set Action Qualifier Control Register For Output A Action Qualifier Control Register For Output B Action Qualifier Software Force Register Action Qualifier Continuous S/W Force Register Set Dead-Band Generator Control Register Dead-Band Generator Rising Edge Delay Count Register Dead-Band Generator Falling Edge Delay Count Register Trip Zone Select Register (1) Trip Zone Control Register (1) Trip Zone Enable Interrupt Register (1) Trip Zone Flag Register Trip Zone Clear Register (1) Trip Zone Force Register (1) Event Trigger Selection Register Event Trigger Prescale Register Event Trigger Flag Register Event Trigger Clear Register Event Trigger Force Register PWM Chopper Control Register HRPWM Configuration Register (1) Registers that are EALLOW protected. 56 Peripherals Submit Documentation Feedback Product Folder Link(s): SM320F28335-HT Copyright © 2010, Texas Instruments Incorporated SM320F28335-HT www. ti. com SPRS682 ­ DECEMBER 2010 Table 4-3. ePWM Control and Status Registers (remapped configuration in PF3 - DMA accessible) NAME TBCTL TBSTS TBPHSHR TBPHS TBCTR TBPRD CMPCTL CMPAHR CMPA CMPB AQCTLA AQCTLB AQSFRC AQCSFRC DBCTL DBRED DBFED TZSEL TZCTL TZEINT TZFLG TZCLR TZFRC ETSEL ETPS ETFLG ETCLR ETFRC PCCTL HRCNFG (1) EPWM1 0x5800 0x5801 0x5802 0x5803 0x5804 0x5805 0x5807 0x5808 0x5809 0x580A 0x580B 0x580C 0x580D 0x580E 0x580F 0x5810 0x5811 0x5812 0x5814 0x5815 0x5816 0x5817 0x5818 0x5819 0x581A 0x581B 0x581C 0x581D 0x581E 0x5820 EPWM2 0x5840 0x5841 0x5842 0x5843 0x5844 0x5845 0x5847 0x5848 0x5849 0x584A 0x584B 0x584C 0x584D 0x584E 0x584F 0x5850 0x5851 0x5852 0x5854 0x5855 0x5856 0x5857 0x5858 0x5859 0x585A 0x585B 0x585C 0x585D 0x585E 0x5860 EPWM3 0x5880 0x5881 0x5882 0x5883 0x5884 0x5885 0x5887 0x5888 0x5889 0x588A 0x588B 0x588C 0x588D 0x588E 0x588F 0x5890 0x5891 0x5892 0x5894 0x5895 0x5896 0x5897 0x5898 0x5899 0x589A 0x589B 0x589C 0x589D 0x589E 0x58A0 EPWM4 0x58C0 0x58C1 0x58C2 0x58C3 0x58C4 0x58C5 0x58C7 0x58C8 0x58C9 0x58CA 0x58CB 0x58CC 0x58CD 0x58CE 0x58CF 0x58D0 0x58D1 0x58D2 0x58D4 0x58D5 0x58D6 0x58D7 0x58D8 0x58D9 0x58DA 0x58DB 0x58DC 0x58DD 0x58DE 058E0 EPWM5 0x5900 0x5901 0x5902 0x5903 0x5904 0x5905 0x5907 0x5908 0x5909 0x590A 0x590B 0x590C 0x590D 0x590E 0x590F 0x5910 0x5911 0x5912 0x5914 0x5915 0x5916 0x5917 0x5918 0x5919 0x591A 0x591B 0x591C 0x591D 0x591E 0x5920 EPWM6 0x5940 0x5941 0x5942 0x5943 0x5944 0x5945 0x5947 0x5948 0x5949 0x594A 0x594B 0x594C 0x594D 0x594E 0x594F 0x5950 0x5951 0x5952 0x5954 0x5955 0x5956 0x5957 0x5958 0x5959 0x595A 0x595B 0x595C 0x595D 0x595E 0x5960 SIZE (x16) / #SHADOW 1/0 1/0 1/0 1/0 1/0 1/1 1/0 1/1 1/1 1/1 1/0 1/0 1/0 1/1 1/1 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 DESCRIPTION Time Base Control Register Time Base Status Register Time Base Phase HRPWM Register Time Base Phase Register Time Base Counter Register Time Base Period Register Set Counter Compare Control Register Time Base Compare A HRPWM Register Counter Compare A Register Set Counter Compare B Register Set Action Qualifier Control Register For Output A Action Qualifier Control Register For Output B Action Qualifier Software Force Register Action Qualifier Continuous S/W Force Register Set Dead-Band Generator Control Register Dead-Band Generator Rising Edge Delay Count Register Dead-Band Generator Falling Edge Delay Count Register Trip Zone Select Register (1) Trip Zone Control Register (1) Trip Zone Enable Interrupt Register (1) Trip Zone Flag Register Trip Zone Clear Register (1) Trip Zone Force Register (1) Event Trigger Selection Register Event Trigger Prescale Register Event Trigger Flag Register Event Trigger Clear Register Event Trigger Force Register PWM Chopper Control Register HRPWM Configuration Register (1) Registers that are EALLOW protected. Copyright © 2010, Texas Instruments Incorporated Peripherals Submit Documentation Feedback Product Folder Link(s): SM320F28335-HT 57 SM320F28335-HT SPRS682 ­ DECEMBER 2010 www. ti. com Time-base (TB) TBPRD shadow (16) TBPRD active (16) CTR=PRD TBCTL[CNTLDE] Counter up/down (16 bit) TBCNT active (16) 16 8 Phase control CTR = PRD CTR = ZERO CTR = CMPA CTR = CMPB CTR_Dir Event trigger and interrupt (ET) EPWMxINT EPWMxSOCA EPWMxSOCB EPWMxSYNCI CTR=ZERO CTR_Dir TBPHSHR (8) TBCTL[SWFSYNC] (software forced sync) CTR=ZERO CTR=CMPB Disabled Sync in/out select Mux EPWMxSYNCO TBCTL[SYNCOSEL] TBPHS active (24) Counter compare (CC) CTR=CMPA CMPAHR (8) 16 8 CMPA active (24) Action qualifier (AQ) HiRes PWM (HRPWM) EPWMA EPWMxAO CMPA shadow (24) CTR=CMPB 16 EPWMB CMPB active (16) CMPB shadow (16) CTR = ZERO Dead band (DB) PWM chopper (PC) Trip zone (TZ) EPWMxBO EPWMxTZINT TZ1 to TZ6 Figure 4-5. ePWM Submodules Showing Critical Internal Signal Interconnections 58 Peripherals Submit Documentation Feedback Product Folder Link(s): SM320F28335-HT Copyright © 2010, Texas Instruments Incorporated SM320F28335-HT www. ti. com SPRS682 ­ DECEMBER 2010 4. 4 High-Resolution PWM (HRPWM) The HRPWM module offers PWM resolution (time granularity) which is significantly better than what can be achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are: · Significantly extends the time resolution capabilities of conventionally derived digital PWM · Typically used when effective PWM resolution falls below ~ 9-10 bits. This occurs at PWM frequencies greater than ~200 kHz when using a CPU/System clock of 100 MHz. · This capability can be utilized in both duty cycle and phase-shift control methods. · Finer time granularity control or edge positioning is controlled via extensions to the Compare A and Phase registers of the ePWM module. · HRPWM capabilities are offered only on the A signal path of an ePWM module (i. e. , on the EPWMxA output). EPWMxB output has conventional PWM capabilities. 4. 5 Enhanced CAP Modules (eCAP1/2/3/4/5/6) The F28335 contains up to six enhanced capture (eCAP) modules. Figure 4-6 shows a functional block diagram of a module. Copyright © 2010, Texas Instruments Incorporated Peripherals Submit Documentation Feedback Product Folder Link(s): SM320F28335-HT 59 SM320F28335-HT SPRS682 ­ DECEMBER 2010 www. ti. com SYNCIn SYNCOut SYNC CTRPHS (phase register-32 bit) TSCTR (counter-32 bit) OVF RST 32 CTR [0-31] 32 PRD [0-31] CTR_OVF Delta-mode APWM mode CTR [0-31] PRD [0-31] CMP [0-31] CTR=PRD CTR=CMP PWM compare logic 32 CAP1 (APRD active) APRD shadow 32 32 LD1 LD Polarity select CMP [0-31] 32 CAP2 (ACMP active) 32 LD LD2 Polarity select Event qualifier Event Pre-scale Polarity select ACMP shadow 32 CAP3 (APRD shadow) LD LD3 32 CAP4 (ACMP shadow) LD LD4 Polarity select 4 Capture events CEVT[1:4] Interrupt Trigger and Flag control 4 to PIE CTR_OVF CTR=PRD CTR=CMP Continuous / Oneshot Capture Control Figure 4-6. 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