User manual TEXAS INSTRUMENTS STELLARIS LM3S1165 MICROCONTROLLER DATASHEET

[. . . ] TE X AS INS TRUM E NTS - P RO DUCTI O N D ATA Stellaris® LM3S1165 Microcontroller D ATA SHE E T D S -LM 3S 1165 - 7 7 8 7 C opyri ght © 2007-2010 Texas Instr uments Incor porated Copyright Copyright © 2007-2010 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Products conform to specifications per the terms of Texas Instruments standard warranty. [. . . ] If the unit is unclocked, reads or writes to the unit will generate a bus fault. 218 Texas Instruments-Production Data September 04, 2010 Stellaris® LM3S1165 Microcontroller Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Deep Sleep Mode Clock Gating Control Register 1 (DCGC1) Base 0x400F. E000 Offset 0x124 Type R/W, reset 0x00000000 31 30 29 28 reserved Type Reset RO 0 15 RO 0 14 reserved Type Reset RO 0 RO 0 RO 0 RO 0 13 RO 0 12 I2C0 R/W 0 RO 0 RO 0 RO 0 11 RO 0 10 RO 0 9 reserved RO 0 RO 0 RO 0 RO 0 27 26 25 24 COMP0 R/W 0 8 RO 0 7 23 22 21 20 19 TIMER3 RO 0 4 SSI0 R/W 0 R/W 0 3 reserved 18 TIMER2 R/W 0 2 UART2 R/W 0 17 TIMER1 R/W 0 1 UART1 R/W 0 16 TIMER0 R/W 0 0 UART0 R/W 0 reserved RO 0 6 RO 0 5 SSI1 R/W 0 RO 0 Bit/Field 31:25 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Analog Comparator 0 Clock Gating This bit controls the clock gating for analog comparator 0. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 24 COMP0 R/W 0 23:20 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Timer 3 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 3. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 19 TIMER3 R/W 0 18 TIMER2 R/W 0 Timer 2 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 2. If the unit is unclocked, reads or writes to the unit will generate a bus fault. September 04, 2010 Texas Instruments-Production Data 219 System Control Bit/Field 17 Name TIMER1 Type R/W Reset 0 Description Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 16 TIMER0 R/W 0 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 15:13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C0 Clock Gating Control This bit controls the clock gating for I2C module 0. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 12 I2C0 R/W 0 11:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. [. . . ] 100-Pin LQFP Tape and Reel Dimensions THIS IS A COMPUTER GENERATED UNCONTROLLED DOCUMENT PRINTED ON 06. 01. 2003 06. 01. 2003 06. 01. 2003 MUST NOT BE REPRODUCED WITHOUT WRITTEN PERMISSION FROM SUMICARRIER (S) PTE LTD 06. 01. 2003 06. 01. 2003 660 Texas Instruments-Production Data September 04, 2010 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. [. . . ]