User manual TEXAS INSTRUMENTS STELLARIS LM3S1439 DATA SHEET REV D

[. . . ] TE X AS I NS TRUM E NTS - P RO DUCTION D ATA Stellaris® LM3S1439 Microcontroller D ATA SH E E T D S -LM 3S 1439 - 7 3 9 3 C opyri ght © 2007-2010 Texas Instruments Incorporated Copyright Copyright © 2007-2010 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Products conform to specifications per the terms of Texas Instruments standard warranty. [. . . ] The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as well as the GPIOPCellID0-GPIOPCellID3 registers. 9. 2 Initialization and Configuration To use the GPIO, the peripheral clock must be enabled by setting the appropriate GPIO Port bit field (GPIOn) in the RCGC2 register. On reset, all GPIO pins (except for the five JTAG pins) are configured out of reset to be undriven (tristate): GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0. Table 9-1 on page 179 shows all possible configurations of the GPIO pads and the control register settings required to achieve them. Table 9-2 on page 179 shows how a rising edge interrupt would be configured for pin 2 of a GPIO port. Table 9-1. GPIO Pad Configuration Examples Configuration GPIO Register Bit Value AFSEL Digital Input (GPIO) Digital Output (GPIO) Open Drain Output (GPIO) Open Drain Input/Output (I2C) Digital Input (Timer CCP) Digital Input (QEI) Digital Output (PWM) Digital Output (Timer PWM) Digital Input/Output (SSI) Digital Input/Output (UART) Analog Input (Comparator) Digital Output (Comparator) 0 0 0 1 1 1 1 1 1 1 0 1 DIR 0 1 1 X X X X X X X 0 X a ODR 0 0 1 1 0 0 0 0 0 0 0 0 DEN 1 1 1 1 1 1 1 1 1 1 0 1 PUR ?X=Ignored (don't care bit) ?=Can be either 0 or 1, depending on the configuration Table 9-2. GPIO Interrupt Configuration Example Register Desired Interrupt Event Trigger 0=edge 1=level Pin 2 Bit Value 7 6 a 5 4 3 2 1 0 GPIOIS X X X X X 0 X X June 23, 2010 Texas Instruments-Production Data 179 General-Purpose Input/Outputs (GPIOs) Table 9-2. GPIO Interrupt Configuration Example (continued) Register Desired Interrupt Event Trigger 0=single edge 1=both edges GPIOIEV 0=Low level, or negative edge 1=High level, or positive edge GPIOIM 0=masked 1=not masked a. X=Ignored (don't care bit) 0 0 0 0 0 1 0 0 X X X X X 1 X X Pin 2 Bit Value 7 6 a 5 4 3 2 1 0 GPIOIBE X X X X X 0 X X 9. 3 Register Map Table 9-3 on page 181 lists the GPIO registers. The offset listed is a hexadecimal increment to the register's address, relative to that GPIO port's base address: GPIO Port A: 0x4000. 4000 GPIO Port B: 0x4000. 5000 GPIO Port C: 0x4000. 6000 GPIO Port D: 0x4000. 7000 GPIO Port E: 0x4002. 4000 GPIO Port F: 0x4002. 5000 GPIO Port G: 0x4002. 6000 GPIO Port H: 0x4002. 7000 Important: The GPIO registers in this chapter are duplicated in each GPIO block; however, depending on the block, all eight bits may not be connected to a GPIO pad. In those cases, writing to those unconnected bits has no effect, and reading those unconnected bits returns no meaningful data. Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000. 0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). Because of this, the default reset value of these registers for GPIO Port B is 0x0000. 0080 while the default reset value for Port C is 0x0000. 000F. The default register type for the GPIOCR register is RO for all GPIO pins with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins are currently the only GPIOs that are protected by the GPIOCR register. Because of this, the register type for GPIO Port B7 and GPIO Port C[3:0] is R/W. The default reset value for the GPIOCR register is 0x0000. 00FF for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port is not accidentally programmed as a GPIO, these five pins default to non-committable. 180 Texas Instruments-Production Data June 23, 2010 Stellaris® LM3S1439 Microcontroller Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000. 007F while the default reset value of GPIOCR for Port C is 0x0000. 00F0. GPIO Register Map Offset 0x000 0x400 0x404 0x408 0x40C 0x410 0x414 0x418 0x41C 0x420 0x500 0x504 0x508 0x50C 0x510 0x514 0x518 0x51C 0x520 0x524 0xFD0 0xFD4 0xFD8 0xFDC 0xFE0 0xFE4 0xFE8 0xFEC 0xFF0 0xFF4 Name GPIODATA GPIODIR GPIOIS GPIOIBE GPIOIEV GPIOIM GPIORIS GPIOMIS GPIOICR GPIOAFSEL GPIODR2R GPIODR4R GPIODR8R GPIOODR GPIOPUR GPIOPDR GPIOSLR GPIODEN GPIOLOCK GPIOCR GPIOPeriphID4 GPIOPeriphID5 GPIOPeriphID6 GPIOPeriphID7 GPIOPeriphID0 GPIOPeriphID1 GPIOPeriphID2 GPIOPeriphID3 GPIOPCellID0 GPIOPCellID1 Type R/W R/W R/W R/W R/W R/W RO RO W1C R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO RO RO RO RO Reset 0x0000. 0000 0x0000. 0000 0x0000. 0000 0x0000. 0000 0x0000. 0000 0x0000. 0000 0x0000. 0000 0x0000. 0000 0x0000. 0000 0x0000. 00FF 0x0000. 0000 0x0000. 0000 0x0000. 0000 0x0000. 0000 0x0000. 0000 0x0000. 0001 0x0000. 0000 0x0000. 0000 0x0000. 0000 0x0000. 0000 0x0000. 0061 0x0000. 0000 0x0000. 0018 0x0000. 0001 0x0000. 000D 0x0000. 00F0 Description GPIO Data GPIO Direction GPIO Interrupt Sense GPIO Interrupt Both Edges GPIO Interrupt Event GPIO Interrupt Mask GPIO Raw Interrupt Status GPIO Masked Interrupt Status GPIO Interrupt Clear GPIO Alternate Function Select GPIO 2-mA Drive Select GPIO 4-mA Drive Select GPIO 8-mA Drive Select GPIO Open Drain Select GPIO Pull-Up Select GPIO Pull-Down Select GPIO Slew Rate Control Select GPIO Digital Enable GPIO Lock GPIO Commit GPIO Peripheral Identification 4 GPIO Peripheral Identification 5 GPIO Peripheral Identification 6 GPIO Peripheral Identification 7 GPIO Peripheral Identification 0 GPIO Peripheral Identification 1 GPIO Peripheral Identification 2 GPIO Peripheral Identification 3 GPIO PrimeCell Identification 0 GPIO PrimeCell Identification 1 See page 183 184 185 186 187 188 189 190 191 192 194 195 196 197 198 199 200 201 202 203 205 206 207 208 209 210 211 212 213 214 June 23, 2010 Texas Instruments-Production Data 181 General-Purpose Input/Outputs (GPIOs) Table 9-3. GPIO Register Map (continued) Offset 0xFF8 0xFFC Name GPIOPCellID2 GPIOPCellID3 Type RO RO Reset 0x0000. 0005 0x0000. 00B1 Description GPIO PrimeCell Identification 2 GPIO PrimeCell Identification 3 See page 215 216 9. 4 Register Descriptions The remainder of this section lists and describes the GPIO registers, in numerical order by address offset. 182 Texas Instruments-Production Data June 23, 2010 Stellaris® LM3S1439 Microcontroller Register 1: GPIO Data (GPIODATA), offset 0x000 The GPIODATA register is the data register. In software control mode, values written in the GPIODATA register are transferred onto the GPIO port pins if the respective pins have been configured as outputs through the GPIO Direction (GPIODIR) register (see page 184). In order to write to GPIODATA, the corresponding bits in the mask, resulting from the address bus bits [9:2], must be High. [. . . ] 108-Ball BGA Package 566 Texas Instruments-Production Data June 23, 2010 Stellaris® LM3S1439 Microcontroller Note: The following notes apply to the package drawing. Symbols A A1 A3 c D D1 E E1 b bbb ddd e f M n MIN 1. 22 0. 29 0. 65 0. 28 9. 85 NOM 1. 36 0. 34 0. 70 0. 32 10. 00 8. 80 BSC MAX 1. 50 0. 39 0. 75 0. 36 10. 15 9. 85 10. 00 8. 80 BSC 10. 15 0. 43 0. 48 . 20 . 12 0. 80 BSC 0. 53 - 0. 60 12 108 REF: JEDEC MO-219F - June 23, 2010 Texas Instruments-Production Data 567 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. [. . . ]