User manual TEXAS INSTRUMENTS TMS320C28343 DATA MANUAL REV B

[. . . ] TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 Delfino Microcontrollers Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Literature Number: SPRS516B March 2009 ­ Revised July 2010 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516B ­ MARCH 2009 ­ REVISED JULY 2010 www. ti. com Contents 1 TMS320C2834x ( DelfinoTM) MCUs 2 3 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [. . . ] On the C28x, the JTAG port can still function even if the CPU clock (CLKIN) is turned off. The various low-power modes operate as follows: IDLE Mode: This mode is exited by any enabled interrupt or an XNMI that is recognized by the processor. The LPM block performs no tasks during this mode as long as the LPMCR0(LPM) bits are set to 0, 0. Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY mode. The user must select which signal(s) will wake the device in the GPIOLPMSEL register. The selected signal(s) are also qualified by the OSCCLK before waking the device. Only the XRS and any GPIO port A signal (GPIO[31:0]) can wake the device from HALT mode. NOTE The low-power modes do not affect the state of the output pins (PWM pins included). They will be in whatever state the code left them in when the IDLE instruction was executed. See the TMS320x2834x Delfino System Control and Interrupts Reference Guide (literature number SPRUFN1) for more details. STANDBY Mode: HALT Mode: Copyright © 2009­2010, Texas Instruments Incorporated Functional Overview Submit Documentation Feedback Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 61 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516B ­ MARCH 2009 ­ REVISED JULY 2010 www. ti. com 4 Peripherals The integrated peripherals are described in the following subsections: · 6-channel Direct Memory Access (DMA) · Three 32-bit CPU-Timers · Up to nine enhanced PWM modules (ePWM1, ePWM2, ePWM3, ePWM4, ePWM5, ePWM6, ePWM7, ePWM8, ePWM9) · Up to six enhanced capture modules (eCAP1, eCAP2, eCAP3, eCAP4, eCAP5, eCAP6) · Up to three enhanced QEP modules (eQEP1, eQEP2, eQEP3) · External analog-to-digital converter (ADC) Interface · Up to two enhanced controller area network (eCAN) modules (eCAN-A, eCAN-B) · Up to three serial communications interface modules (SCI-A, SCI-B, SCI-C) · Up to two serial peripheral interface (SPI) modules (SPI-A, SPI-D) · Inter-integrated circuit module (I2C) · Up to two multichannel buffered serial port (McBSP-A, McBSP-B) modules · Digital I/O and shared pin functions · External Interface (XINTF) 4. 1 DMA Overview Features: · 6 Channels with independent PIE interrupts · Trigger Sources: ­ McBSP-A and McBSP-B transmit and receive logic ­ XINT1­7 and XINT13 ­ CPU Timers ­ Software · Data Sources/Destinations: ­ L0­L7 64K × 16 SARAM ­ All XINTF zones ­ McBSP-A and McBSP-B transmit and receive buffers · Word Size: 16-bit or 32-bit (McBSPs limited to 16-bit) · Throughput: 4 cycles/word (5 cycles/word for McBSP reads) 62 Peripherals Copyright © 2009­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www. ti. com SPRS516B ­ MARCH 2009 ­ REVISED JULY 2010 CPU bus L0 I/F L1 I/F INT7 External interrupts CPU timers PIE L0 RAM L1 RAM L2 RAM L3 RAM L4 RAM L5 RAM L6 RAM L7 RAM XINTF zones interface XINTF memory zones L2 I/F L3 I/F L4 I/F L5 I/F L6 I/F L7 I/F DINT[CH1:CH6] McBSP A PF3 I/F McBSP B Event triggers DMA 6-ch DMA bus CPU Figure 4-1. DMA Functional Block Diagram Copyright © 2009­2010, Texas Instruments Incorporated Peripherals Submit Documentation Feedback Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 63 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516B ­ MARCH 2009 ­ REVISED JULY 2010 www. ti. com 4. 2 32-Bit CPU-Timers 0/1/2 There are three 32-bit CPU-timers on the devices (CPU-TIMER0/1/2). These timers are different from the timers that are present in the ePWM modules. NOTE NOTE: If the application is not using DSP/BIOS, then CPU-Timer 2 can be used in the application. Reset Timer Reload 16-Bit Timer Divide-Down TDDRH:TDDR 32-Bit Timer Period PRDH:PRD SYSCLKOUT TCR. 4 (Timer Start Status) 16-Bit Prescale Counter PSCH:PSC Borrow 32-Bit Counter TIMH:TIM Borrow TINT Figure 4-2. CPU-Timers The timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in Figure 4-3. INT1 to INT12 PIE TINT0 CPU-TIMER 0 28x CPU TINT1 INT13 XINT13 INT14 TINT2 CPU-TIMER 2 (Reserved for DSP/BIOS) CPU-TIMER 1 A. B. The timer registers are connected to the memory bus of the C28x processor. The timing of the timers is synchronized to SYSCLKOUT of the processor clock. Figure 4-3. CPU-Timer Interrupt Signals and Output Signal 64 Peripherals Copyright © 2009­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www. ti. com SPRS516B ­ MARCH 2009 ­ REVISED JULY 2010 The general operation of the timer is as follows: The 32-bit counter register "TIMH:TIM" is loaded with the value in the period register "PRDH:PRD". When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. For more information, see the TMS320x2834x Delfino System Control and Interrupts Reference Guide (literature number SPRUFN1). CPU-Timers 0, 1, 2 Configuration and Control Registers NAME TIMER0TIM TIMER0TIMH TIMER0PRD TIMER0PRDH TIMER0TCR Reserved TIMER0TPR TIMER0TPRH TIMER1TIM TIMER1TIMH TIMER1PRD TIMER1PRDH TIMER1TCR Reserved TIMER1TPR TIMER1TPRH TIMER2TIM TIMER2TIMH TIMER2PRD TIMER2PRDH TIMER2TCR Reserved TIMER2TPR TIMER2TPRH Reserved ADDRESS 0x0C00 0x0C01 0x0C02 0x0C03 0x0C04 0x0C05 0x0C06 0x0C07 0x0C08 0x0C09 0x0C0A 0x0C0B 0x0C0C 0x0C0D 0x0C0E 0x0C0F 0x0C10 0x0C11 0x0C12 0x0C13 0x0C14 0x0C15 0x0C16 0x0C17 0x0C18 ­ 0x0C3F SIZE (x16) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 40 CPU-Timer 2, Prescale Register CPU-Timer 2, Prescale Register High CPU-Timer 1, Prescale Register CPU-Timer 1, Prescale Register High CPU-Timer 2, Counter Register CPU-Timer 2, Counter Register High CPU-Timer 2, Period Register CPU-Timer 2, Period Register High CPU-Timer 2, Control Register CPU-Timer 0, Prescale Register CPU-Timer 0, Prescale Register High CPU-Timer 1, Counter Register CPU-Timer 1, Counter Register High CPU-Timer 1, Period Register CPU-Timer 1, Period Register High CPU-Timer 1, Control Register CPU-Timer 0, Counter Register CPU-Timer 0, Counter Register High CPU-Timer 0, Period Register CPU-Timer 0, Period Register High CPU-Timer 0, Control Register DESCRIPTION Copyright © 2009­2010, Texas Instruments Incorporated Peripherals Submit Documentation Feedback Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 65 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516B ­ MARCH 2009 ­ REVISED JULY 2010 www. ti. com 4. 3 Enhanced PWM Modules (ePWM1/2/3/4/5/6 /7/8/9) The devices contain up to nine enhanced PWM Modules (ePWM). Table 4-2 and Table 4-3 show the complete ePWM register set per module. EXTSOC1A POLSEL 0 EXTSOC1A ePWM1SOCA ePWM1 ePWM1SOCB ePWM2SOCA ePWM2 ePWM2SOCB ePWM3SOCA ePWM3 ePWM3SOCB ePWM4SOCA ePWM4 0 ePWM4SOCB ePWM5SOCA ePWM5 ePWM5SOCB ePWM6SOCA ePWM6 ePWM6SOCB 1 ePWM7SOCA ePWM7 ePWM7SOCB ePWM8SOCA ePWM8 ePWM8SOCB ePWM9SOCA ePWM9 ePWM9SOCB 1 EXTSOC3B POLSEL 0 EXTSOC3B 1 EXTSOC3A POLSEL 0 EXTSOC3A 1 EXTSOC2B POLSEL 0 0 1 EXTSOC2A POLSEL EXTSOC1B 1 EXTSOC1B POLSEL Pulse Stretcher, 32 HSPCLK Cycles Wide and Then to Chip Pins EXTSOC2A EXTSOC2B Figure 4-4. Generation of SOC Pulses to the External ADC Module 66 Peripherals Copyright © 2009­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 www. ti. com SPRS516B ­ MARCH 2009 ­ REVISED JULY 2010 Table 4-2. ePWM1-4 Control and Status Registers NAME TBCTL TBSTS TBPHSHR TBPHS TBCTR TBPRD CMPCTL CMPAHR CMPA CMPB AQCTLA AQCTLB AQSFRC AQCSFRC DBCTL DBRED DBFED TZSEL TZCTL TZEINT TZFLG TZCLR TZFRC ETSEL ETPS ETFLG ETCLR ETFRC PCCTL HRCNFG (1) ePWM1 0x6800 0x6801 0x6802 0x6803 0x6804 0x6805 0x6807 0x6808 0x6809 0x680A 0x680B 0x680C 0x680D 0x680E 0x680F 0x6810 0x6811 0x6812 0x6814 0x6815 0x6816 0x6817 0x6818 0x6819 0x681A 0x681B 0x681C 0x681D 0x681E 0x6820 ePWM2 0x6840 0x6841 0x6842 0x6843 0x6844 0x6845 0x6847 0x6848 0x6849 0x684A 0x684B 0x684C 0x684D 0x684E 0x684F 0x6850 0x6851 0x6852 0x6854 0x6855 0x6856 0x6857 0x6858 0x6859 0x685A 0x685B 0x685C 0x685D 0x685E 0x6860 ePWM3 0x6880 0x6881 0x6882 0x6883 0x6884 0x6885 0x6887 0x6888 0x6889 0x688A 0x688B 0x688C 0x688D 0x688E 0x688F 0x6890 0x6891 0x6892 0x6894 0x6895 0x6896 0x6897 0x6898 0x6899 0x689A 0x689B 0x689C 0x689D 0x689E 0x68A0 ePWM4 0x68C0 0x68C1 0x68C2 0x68C3 0x68C4 0x68C5 0x68C7 0x68C8 0x68C9 0x68CA 0x68CB 0x68CC 0x68CD 0x68CE 0x68CF 0x68D0 0x68D1 0x68D2 0x68D4 0x68D5 0x68D6 0x68D7 0x68D8 0x68D9 0x68DA 0x68DB 0x68DC 0x68DD 0x68DE 0x68E0 SIZE (x16) / #SHADOW 1/0 1/0 1/0 1/0 1/0 1/1 1/0 1/1 1/1 1/1 1/0 1/0 1/0 1/1 1/1 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 Time Base Control Register Time Base Status Register Time Base Phase HRPWM Register Time Base Phase Register Time Base Counter Register Time Base Period Register Set Counter Compare Control Register Time Base Compare A HRPWM Register Counter Compare A Register Set Counter Compare B Register Set Action Qualifier Control Register For Output A Action Qualifier Control Register For Output B Action Qualifier Software Force Register Action Qualifier Continuous S/W Force Register Set Dead-Band Generator Control Register Dead-Band Generator Rising Edge Delay Count Register Dead-Band Generator Falling Edge Delay Count Register Trip Zone Select Register Trip Zone Control Register Trip Zone Enable Interrupt Register Trip Zone Flag Register Trip Zone Clear Register Trip Zone Force Register Event Trigger Selection Register Event Trigger Prescale Register Event Trigger Flag Register Event Trigger Clear Register Event Trigger Force Register PWM Chopper Control Register HRPWM Configuration Register (1) DESCRIPTION Registers that are EALLOW protected. Copyright © 2009­2010, Texas Instruments Incorporated Peripherals 67 Submit Documentation Feedback Product Folder Link(s): TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516B ­ MARCH 2009 ­ REVISED JULY 2010 www. ti. com Table 4-3. [. . . ] In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. [. . . ]