User manual TEXAS INSTRUMENTS TMS320C5505 DATASHEET 08-2010

[. . . ] TMS320C5505 www. ti. com SPRS660B ­ AUGUST 2010 ­ REVISED AUGUST 2010 TMS320C5505 Fixed-Point Digital Signal Processor Check for Samples: TMS320C5505 1 Fixed-Point Digital Signal Processor 1. 1 12 Features ­ Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses ­ Software-Compatible With C55x Devices ­ Industrial Temperature Devices Available 320K Bytes Zero-Wait State On-Chip RAM, Composed of: ­ 64K Bytes of Dual-Access RAM (DARAM), 8 Blocks of 4K x 16-Bit ­ 256K Bytes of Single-Access RAM (SARAM), 32 Blocks of 4K x 16-Bit 128K Bytes of Zero Wait-State On-Chip ROM (4 Blocks of 16K x 16-Bit) 4M x 16-Bit Maximum Addressable External Memory Space (SDRAM/mSDRAM) 16-/8-Bit External Memory Interface (EMIF) with Glueless Interface to: ­ 8-/16-Bit NAND Flash, 1- and 4-Bit ECC ­ 8-/16-Bit NOR Flash ­ Asynchronous Static RAM (SRAM) ­ 16-bit SDRAM/mSDRAM (1. 8-, 2. 5-, 2. 75-, and 3. 3-V) Direct Memory Access (DMA) Controller ­ Four DMA With 4 Channels Each (16-Channels Total) Three 32-Bit General-Purpose Timers ­ One Selectable as a Watchdog and/or GP Two MultiMedia Card/Secure Digital (MMC/SD) Interfaces Universal Asynchronous Receiver/Transmitter (UART) Serial-Port Interface (SPI) With Four Chip-Selects Master/Slave Inter-Integrated Circuit (I2C BusTM) Four Inter-IC Sound (I2S BusTM) for Data Transport · HIGHLIGHTS: · High-Perf/Low-Power, C55xTM Fixed-Point DSP ­ 16. 67/13. 33/10/8. 33/6. 66-ns Instruction Cycle Time ­ 60-, 75-, 100-, 120-, 150-MHz Clock Rate · 320K Bytes On-Chip RAM · 16-/8-Bit External Memory Interface (EMIF) · Two MultiMedia Card/Secure Digital I/Fs · Serial-Port I/F (SPI) With Four Chip-Selects · Four Inter-IC Sound (I2S BusTM) · USB 2. 0 Full- and High-Speed Device · LCD Bridge With Asynchronous Interface · Tightly-Coupled FFT Hardware Accelerator · 10-Bit 4-Input Successive Approximation (SAR) ADC · Real-Time Clock (RTC) With Crystal Input · Four Core Isolated Power Supply Domains · Four I/O Isolated Power Supply Domains · One Integrated LDO · Industrial Temperature Devices Available · 1. 05-V Core, 1. 8/2. 5/2. 75/3. 3-V I/Os · 1. 3-V Core, 1. 8/2. 5/2. 75/3. 3-V I/Os · 1. 4-V Core, 1. 8/2. 5/2. 75/3. 3-V I/Os · FEATURES: · High-Performance, Low-Power, TMS320C55xTM Fixed-Point Digital Signal Processor ­ 16. 67-, 13. 33-, 10-, 8. 33-, 6. 66-ns Instruction Cycle Time ­ 60-, 75-, 100-, 120-, 150-MHz Clock Rate ­ One/Two Instruction(s) Executed per Cycle ­ Dual Multipliers [Up to 200, 240, or 300 Million Multiply-Accumulates per Second (MMACS)] ­ Two Arithmetic/Logic Units (ALUs) · · · · · · · · · · · 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2010, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TMS320C5505 SPRS660B ­ AUGUST 2010 ­ REVISED AUGUST 2010 www. ti. com · Device USB Port With Integrated 2. 0 High-Speed PHY that Supports: ­ USB 2. 0 Full- and High-Speed Device · LCD Bridge With Asynchronous Interface · Tightly-Coupled FFT Hardware Accelerator · 10-Bit 4-Input Successive Approximation (SAR) ADC · Real-Time Clock (RTC) With Crystal Input, With Separate Clock Domain, Separate Power Supply · Four Core Isolated Power Supply Domains: Analog, RTC, CPU and Peripherals, and USB · Four I/O Isolated Power Supply Domains: RTC I/O, EMIF I/O, USB PHY, and DVDDIO · One integrated LDO (ANA_LDO) to power DSP PLL (VDDA_PLL) and 10-bit SAR ADC (VDDA_ANA) · Low-Power S/W Programmable Phase-Locked Loop (PLL) Clock Generator · On-Chip ROM Bootloader (RBL) to Boot From NAND Flash, NOR Flash, SPI EEPROM, SPI Serial Flash or I2C EEPROM · IEEE-1149. 1 (JTAGTM) Boundary-Scan-Compatible · Up to 26 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions) · 196-Terminal Pb-Free Plastic BGA (Ball Grid Array) (ZCH Suffix) · 1. 05-V Core (60 or 75 MHz), 1. 8-V, 2. 5-V, 2. 75-V, or 3. 3-V I/Os · 1. 3-V Core (100, 120 MHz), 1. 8-V, 2. 5-V, 2. 75-V, or 3. 3-V I/Os · 1. 4-V Core (150 MHz), 1. 8-V, 2. 5-V, 2. 75-V or 3. 3-V I/Os · Applications: ­ Wireless Audio Devices (e. g. , Headsets, Microphones, Speakerphones, etc. ) ­ Echo Cancellation Headphones ­ Portable Medical Devices ­ Voice Applications ­ Industrial Controls ­ Fingerprint Biometrics ­ Software Defined Radio · Community Resources ­ TI E2E Community ­ TI Embedded Processors Wiki 2 Fixed-Point Digital Signal Processor Submit Documentation Feedback Product Folder Link(s): TMS320C5505 Copyright © 2010, Texas Instruments Incorporated TMS320C5505 www. ti. com SPRS660B ­ AUGUST 2010 ­ REVISED AUGUST 2010 1. 2 Description The device is a member of TI's TMS320C5000TM fixed-point Digital Signal Processor (DSP) product family and is designed for low-power applications. [. . . ] The internal POR monitors the DSP_LDOO pin voltage and generates the internal POWERGOOD signal. The internal POWERGOOD signal is forced high and the external reset signal on the RESET pin (D6) is the only source of the device reset. Note: DSP_LDO can be enabled only to support the RTC only mode (see Section 6. 11. 1, RTC Only Mode for details), otherwise, DSP_LDO should be disabled on this device. DSP_LDO output must never be used to provide power to the CPU Core (CVDD) on this device. 0 = 32-KHz on-chip oscillator drives the RTC timer and the DSP clock generator. 1 = CLKIN drives the DSP clock generator and the 32-KHz on-chip oscillator drives only the RTC timer. This pin is not allowed to change during device operation; it must be tied to DVDDIO or GND at the board. CLK_SEL C7 ­ For proper device operation, external pullup/pulldown resistors may be required on these device configuration pins. For discussion on situations where external pullup/pulldown resistors are required, see Section 4. 8. 1, Pullup/Pulldown Resistors. This device also has RESERVED pins that need to be configured correctly for proper device operation (statically tied high, tied low, or left unconnected at all times). For more details on these pins, see Table 3-20, Reserved and No Connects Terminal Functions. 4. 6 Configurations After Reset The following sections provide details on configuring the device after reset. For more details on multiplexed pin function control, see Section 4. 7, Multiplexed Pin Configurations. 4. 6. 1 External Bus Selection Register (EBSR) The External Bus Selection Register (EBSR) determines the mapping of the LCD controller, I2S2, I2S3, UART, SPI, and GPIO signals to 21 signals of the external parallel port pins. It also determines the mapping of the I2S or MMC/SD ports to serial port 1 pins and serial port 2 pins. Once the bit fields of this register are changed, the routing of the signals takes place on the next CPU clock cycle. 52 Device Configuration Submit Documentation Feedback Product Folder Link(s): TMS320C5505 Copyright © 2010, Texas Instruments Incorporated TMS320C5505 www. ti. com SPRS660B ­ AUGUST 2010 ­ REVISED AUGUST 2010 Additionally, the EBSR controls the function of the upper bits of the EMIF address bus. Pins EM_A[20:15] can be individually configured as GPIO pins through the Axx_MODE bits. Before modifying the values of the external bus selection register, you must clock gate all affected peripherals through the Peripheral Clock Gating Control Register. After the external bus selection register has been modified, you must reset the peripherals before using them through the Peripheral Software Reset Counter Register. After the boot process is complete, the external bus selection register must be modified only once, during device configuration. Continuously switching the EBSR configuration is not supported. 15 Reserved 14 PPMODE 12 R/W-000 11 R/W-00 10 SP1MODE 9 SP0MODE 8 R/W-00 R-0 7 Reserved 6 Reserved 5 A20_MODE 4 A19_MODE 3 A18_MODE 2 A17_MODE 1 A16_MODE 0 A15_MODE R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 4-2. EBSR Register Bit Descriptions BIT 15 NAME RESERVED DESCRIPTION Reserved. These bits control the pin multiplexing of the LCD Controller, SPI, UART, I2S2, I2S3, and GP[31:27, 20:18] pins on the parallel port. For more details, see , LCD Controller, SPI, UART, I2S2, I2S3, and GP[31:27, 20:18] Pin Multiplexing. All 21 signals of the LCD Bridge module are routed to the 21 external signals of the parallel port. [. . . ] In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE OPTION ADDENDUM www. ti. com 1-Sep-2010 Addendum-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. [. . . ]