User manual TEXAS INSTRUMENTS TMS320C5515 DATASHEET 08-2010

[. . . ] TMS320C5515 www. ti. com SPRS645B ­ AUGUST 2010 ­ REVISED AUGUST 2010 TMS320C5515 Fixed-Point Digital Signal Processor Check for Samples: TMS320C5515 1 Fixed-Point Digital Signal Processor 1. 1 12 Features and Two Internal Data/Operand Write Buses ­ Software-Compatible With C55x Devices ­ Industrial Temperature Devices Available 320K Bytes Zero-Wait State On-Chip RAM, Composed of: ­ 64K Bytes of Dual-Access RAM (DARAM), 8 Blocks of 4K x 16-Bit ­ 256K Bytes of Single-Access RAM (SARAM), 32 Blocks of 4K x 16-Bit 128K Bytes of Zero Wait-State On-Chip ROM (4 Blocks of 16K x 16-Bit) 4M x 16-Bit Maximum Addressable External Memory Space (SDRAM/mSDRAM) 16-/8-Bit External Memory Interface (EMIF) with Glueless Interface to: ­ 8-/16-Bit NAND Flash, 1- and 4-Bit ECC ­ 8-/16-Bit NOR Flash ­ Asynchronous Static RAM (SRAM) ­ SDRAM/mSDRAM (1. 8-, 2. 5-, 2. 75-, and 3. 3-V) Direct Memory Access (DMA) Controller ­ Four DMA With 4 Channels Each (16-Channels Total) Three 32-Bit General-Purpose Timers ­ One Selectable as a Watchdog and/or GP Two MultiMedia Card/Secure Digital (MMC/SD) Interfaces Universal Asynchronous Receiver/Transmitter (UART) Serial-Port Interface (SPI) With Four Chip-Selects Master/Slave Inter-Integrated Circuit (I2C BusTM) Four Inter-IC Sound (I2S BusTM) for Data Transport · HIGHLIGHTS: · High-Perf/Low-Power, C55xTM Fixed-Point DSP ­ 16. 67/13. 33/10/8. 33-ns Instruction Cycle Time ­ 60-, 75-, 100-, 120-MHz Clock Rate · 320K Bytes On-Chip RAM · 16-/8-Bit External Memory Interface (EMIF) · Two MultiMedia Card/Secure Digital I/Fs · Serial-Port I/F (SPI) With Four Chip-Selects · Four Inter-IC Sound (I2S BusTM) · USB 2. 0 Full- and High-Speed Device · LCD Bridge With Asynchronous Interface · Tightly-Coupled FFT Hardware Accelerator · 10-Bit 4-Input Successive Approximation (SAR) ADC · Real-Time Clock (RTC) With Crystal Input · Four Core Isolated Power Supply Domains · Four I/O Isolated Power Supply Domains · Three Integrated LDOs · Industrial Temperature Devices Available · 1. 05-V Core, 1. 8/2. 5/2. 75/3. 3-V I/Os · 1. 3-V Core, 1. 8/2. 5/2. 75/3. 3-V I/Os · FEATURES: · High-Performance, Low-Power, TMS320C55xTM Fixed-Point Digital Signal Processor ­ 16. 67-, 13. 33-, 10-, 8. 33-ns Instruction Cycle Time ­ 60-, 75-, 100-, 120-MHz Clock Rate ­ One/Two Instruction(s) Executed per Cycle ­ Dual Multipliers [Up to 200 or 240 Million Multiply-Accumulates per Second (MMACS)] ­ Two Arithmetic/Logic Units (ALUs) ­ Three Internal Data/Operand Read Buses · · · · · · · · · · · 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2010, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TMS320C5515 SPRS645B ­ AUGUST 2010 ­ REVISED AUGUST 2010 www. ti. com · Device USB Port With Integrated 2. 0 High-Speed PHY that Supports: ­ USB 2. 0 Full- and High-Speed Device · LCD Bridge With Asynchronous Interface · Tightly-Coupled FFT Hardware Accelerator · 10-Bit 4-Input Successive Approximation (SAR) ADC · Real-Time Clock (RTC) With Crystal Input, With Separate Clock Domain, Separate Power Supply · Four Core Isolated Power Supply Domains: Analog, RTC, CPU and Peripherals, and USB · Four I/O Isolated Power Supply Domains: RTC I/O, EMIF I/O, USB PHY, and DVDDIO · Three integrated LDOs (DSP_LDO, ANA_LDO, and USB_LDO) to power the isolated domains: DSP Core, Analog, and USB Core, respectively · Low-Power S/W Programmable Phase-Locked Loop (PLL) Clock Generator · On-Chip ROM Bootloader (RBL) to Boot From NAND Flash, NOR Flash, SPI EEPROM, SPI Serial Flash or I2C EEPROM · IEEE-1149. 1 (JTAGTM) Boundary-Scan-Compatible · Up to 26 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions) · 196-Terminal Pb-Free Plastic BGA (Ball Grid Array) (ZCH Suffix) · 1. 05-V Core (60 or 75 MHz), 1. 8-V, 2. 5-V, 2. 75-V, or 3. 3-V I/Os · 1. 3-V Core (100, 120 MHz), 1. 8-V, 2. 5-V, 2. 75-V, or 3. 3-V I/Os · Applications: ­ Wireless Audio Devices (e. g. , Headsets, Microphones, Speakerphones, etc. ) ­ Echo Cancellation Headphones ­ Portable Medical Devices ­ Voice Applications ­ Industrial Controls ­ Fingerprint Biometrics ­ Software Defined Radio · Community Resources ­ TI E2E Community ­ TI Embedded Processors Wiki 2 Fixed-Point Digital Signal Processor Submit Documentation Feedback Product Folder Link(s): TMS320C5515 Copyright © 2010, Texas Instruments Incorporated TMS320C5515 www. ti. com SPRS645B ­ AUGUST 2010 ­ REVISED AUGUST 2010 1. 2 Description The device is a member of TI's TMS320C5000TM fixed-point Digital Signal Processor (DSP) product family and is designed for low-power applications. [. . . ] Start Timer0 to Count 200 ms Yes Copy Boot Image Sections to System Memory USB Boot ?Bootloader Software Architecture 4. 4. 1 Boot Modes The device DSP supports the following boot modes in the following device order: NOR Flash, NAND Flash, SPI 16-bit EEPROM, SPI 24-bit Flash, I2C EEPROM, and MMC/SD card. The boot mode is determined by checking for a valid boot signature on each supported boot device. The first boot device with a valid boot signature will be used to load and execute the user code. If none of the supported boot devices have a valid boot signature, the Bootloader goes into an endless loop checking the USB boot mode and the device must be reset to look for another valid boot image in the supported boot modes. Note: For detailed information on MMC/SD and USB boot modes, contact your local sales representative. Copyright © 2010, Texas Instruments Incorporated Device Configuration Submit Documentation Feedback Product Folder Link(s): TMS320C5515 51 TMS320C5515 SPRS645B ­ AUGUST 2010 ­ REVISED AUGUST 2010 www. ti. com 4. 4. 2 Boot Configuration After reset, the on-chip Bootloader programs the system clock generator based on the input clock selected via the CLK_SEL pin. If CLK_SEL = 0, the Bootloader programs the system clock generator and sets the system clock to 12. 288 MHz (multiply the 32. 768-KHz RTC oscillator clock by 375). If CLK_SEL = 1, the Bootloader bypasses the system clock generator altogether and the system clock is driven by the CLKIN pin. Note: · When CLK_SEL =1, the CLKIN frequency is expected to be 11. 2896 MHz, 12. 0 MHz, or 12. 288 MHz. · The on-chip Bootloader allows for DSP registers to be configured during the boot process. However, this feature must not be used to change the output frequency of the system clock generator during the boot process. Timer0 is also used by the bootloader to allow for 200 ms of BG_CAP settling time. The bootloader register modification feature must not modify the Timer0 registers. During the boot process, the bootloader queries each peripheral to determine if it can boot from that peripheral. At that time, the individual peripheral clocks will be enabled for the query and then disabled when the bootloader is finished with the peripheral. By the time the bootloader releases control to the user code, all peripheral clocks will be "off" and all domains in the ICR, except the CPU domain, will be idled. 4. 4. 3 DSP Resources Used By the Bootloader The Bootloader uses SARAM block 31 for the storing of temporary data. However, after the boot process is complete, it can be used by the user application. 52 Device Configuration Submit Documentation Feedback Product Folder Link(s): TMS320C5515 Copyright © 2010, Texas Instruments Incorporated TMS320C5515 www. ti. com SPRS645B ­ AUGUST 2010 ­ REVISED AUGUST 2010 4. 5 Configurations at Reset Some device configurations are determined at reset. The following subsections give more details. 4. 5. 1 Device and Peripheral Configurations at Device Reset Table 4-5 summarizes the device boot and configuration pins that are required to be statically tied high, tied low, or left unconnected during device operation. For proper device operation, a device reset should be initiated after changing any of these pin functions. Default Functions Affected by Device Configuration Pins CONFIGURATION PINS DSP_LDO_EN SIGNAL NO. The internal DSP LDO is enabled to regulate power on the DSP_LDOO pin at either 1. 3 V or 1. 05 V according to the LDO_DSP_V bit in the LDOCNTL register, see Figure 4-2). At power-on-reset, the internal POR monitors the DSP_LDOO pin voltage and generates the internal POWERGOOD signal when the DSP_LDO voltage is above a minimum threshold voltage. [. . . ] In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE OPTION ADDENDUM www. ti. com 13-Aug-2010 Addendum-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. [. . . ]