User manual TEXAS INSTRUMENTS TMS320C6457 DATA MANUAL REV B

[. . . ] TMS320C6457 Communications Infrastructure Digital Signal Processor Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Literature Number: SPRS582B July 2010 TMS320C6457 Data Manual SPRS582B--July 2010 www. ti. com Release History Additions/Modifications/Deletions SPRS582B · Added 850 mHz clock speed. · Added content to the Warm Reset section describing how to preserve contents of DDR2 SDRAM through a Warm Reset cycle with Self-Refresh mode enabled on the SDRAM. [. . . ] The interrupt controller allows for up to 128 system events to be programmed to any of the twelve CPU interrupt inputs (CPUINT4 - CPUINT15), the CPU exception input (EXCEP), or the advanced emulation logic. The 128 system events consist of both internally-generated events (within the megamodule) and chip-level events. For more information on the Interrupt Controller, see the TMS320C64x+ Megamodule Reference Guide (literature number SPRU871). Table 7-12 (1) (1) TMS320C6457 System Event Mapping (Part 1 of 3) Interrupt Event EVT0 EVT1 EVT2 EVT3 Reserved EMU_DTDMA Description Output of event combiner 0 in interrupt controller, for events 1 - 31. Output of event combiner 1 in interrupt controller, for events 32 - 63. Output of event combiner 2 in interrupt controller, for events 64 - 95. Output of event combiner 3 in interrupt controller, for events 96 - 127. EMU interrupt for: · Host scan access · DTDMA transfer complete · AET interrupt This system event is not connected and, therefore, not used. EMU real-time data exchange (RTDX) receive complete EMU RTDX transmit complete IDMA channel 0 interrupt IDMA channel 1 interrupt HPI-to-DSP interrupt I2C interrupt Ethernet MAC interrupt EMIFA error interrupt Reserved. RapidIO interrupt 0 RapidIO interrupt 1 RapidIO interrupt 2 RapidIO interrupt 3 EDMA3 channel global completion interrupt Ethernet MAC receive interrupt Ethernet MAC transmit interrupt Ethernet MAC receive threshold interrupt RapidIO interrupt 4 RapidIO interrupt 5 RapidIO interrupt 6 Reserved. VCP2 error interrupt TCP2_A error interrupt TCP2_B error interrupt Reserved. UTOPIA interrupt Event Number 0 PRODUCT PREVIEW 120 1 2 (1) 3 (1) 4-8 9 (1) 10 11 12 (1) (1) None EMU_RTDXRX EMU_RTDXTX IDMA0 IDMA1 DSPINT I2CINT MACINT AEASYNCERR Reserved INTDST0 INTDST1 INTDST2 INTDST3 EDMA3CC_GINT MACRXINT MACTXINT MACTHRESH INTDST4 INTDST5 INTDST6 Reserved VCP2_INT TCP2A_INT TCP2B_INT Reserved UINT 13(1) 14 (1) 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 C64x+ Peripheral Information and Electrical Specifications 2009 Texas Instruments Incorporated TMS320C6457 Communications Infrastructure Digital Signal Processor www. ti. com SPRS582B--July 2010 TMS320C6457 System Event Mapping (Part 2 of 3) Interrupt Event Reserved RINT0 XINT0 RINT1 XINT1 Reserved GPINT0 GPINT1 GPINT2 GPINT3 GPINT4 GPINT5 GPINT6 GPINT7 GPINT8 GPINT9 GPINT10 GPINT11 GPINT12 GPINT13 GPINT14 GPINT15 TINTLO0 TINTHI0 TINTLO1 TINTHI1 EDMA3CC_INT0 EDMA3CC_INT1 EDMA3CC_INT2 EDMA3CC_INT3 EDMA3CC_INT4 EDMA3CC_INT5 EDMA3CC_INT6 EDMA3CC_INT7 EDMA3CC_ERRINT Reserved EDMA3TC0_ERRINT EDMA3TC1_ERRINT EDMA3TC2_ERRINT EDMA3TC3_ERRINT EDMA3CC_AET EDMA3TC4_ERRINT EDMA3TC5_ERRINT Reserved Description Reserved. McBSP0 receive interrupt McBSP0 transmit interrupt McBSP1 receive interrupt McBSP1 transmit interrupt Reserved. GPIO interrupt GPIO interrupt GPIO interrupt Table 7-12 Event Number 37 - 39 40 41 42 43 44 - 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 - 93 GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt Timer 0 lower counter interrupt Timer 0 higher counter interrupt Timer 1 lower counter interrupt Timer 1 higher counter interrupt EDMA3CC completion interrupt - Mask0 EDMA3CC completion interrupt - Mask1 EDMA3CC completion interrupt - Mask2 EDMA3CC completion interrupt - Mask3 EDMA3CC completion interrupt - Mask4 EDMA3CC completion interrupt - Mask5 EDMA3CC completion interrupt - Mask6 EDMA3CC completion interrupt - Mask7 EDMA3CC error interrupt Reserved. EDMA3TC0 error interrupt EDMA3TC1 error interrupt EDMA3TC2 error interrupt EDMA3TC3 error interrupt EDMA3CC AET Event EDMA3TC4 error interrupt EDMA3TC5 error interrupt Reserved. These system events are not connected and, therefore, not used. 2009 Texas Instruments Incorporated C64x+ Peripheral Information and Electrical Specifications 121 PRODUCT PREVIEW GPIO interrupt TMS320C6457 Communications Infrastructure Digital Signal Processor SPRS582B--July 2010 Table 7-12 TMS320C6457 System Event Mapping (Part 3 of 3) Interrupt Event ETBOVFLINT ETBUNFLINT INTERR EMC_IDMAERR Reserved EFIINTA EFIINTB Reserved L1P_ED1 Reserved L2_ED1 L2_ED2 PDC_INT SYS_CMPA L1P_CMPA L1P_DMPA L1D_CMPA L1D_DMPA L2_CMPA L2_DMPA IDMA_CMPA IDMA_BUSERR Description Overflow condition occurred in ETB Underflow condition occurred in ETB Interrupt Controller dropped CPU interrupt event EMC invalid IDMA parameters Reserved. L2 single bit error detected L2 two bit error detected Powerdown sleep interrupt CPU memory protection fault L1P CPU memory protection fault L1P DMA memory protection fault L1D CPU memory protection fault L1D DMA memory protection fault L2 CPU memory protection fault L2 DMA memory protection fault IDMA CPU memory protection fault IDMA bus error interrupt www. ti. com Event Number 94 95 96 (1) 97 (1) 98 - 99 100 (1) 101 (1) 102 - 112 113 (1) 114 - 115 116 117 (1) (1) PRODUCT PREVIEW No. 1 2 118 (1) 119 120 (1) (1) 121 (1) 122 123 124 125 (1) (1) (1) (1) 126 (1) 127 (1) End of Table 7-12 1 This system event is generated from within the C64x+ megamodule. 7. 5. 2 External Interrupts Electrical Data/Timing Table 7-13 (see Figure 7-8) Min tw(NMIL) tw(NMIH) Width of the NMI interrupt pulse low Width of the NMI interrupt pulse high 6P 6P Max Unit ns ns Timing Requirements for External Interrupts (1) End of Table 7-13 1 P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns. Figure 7-8 NMI Interrupt Timing 1 NMI 2 122 C64x+ Peripheral Information and Electrical Specifications 2009 Texas Instruments Incorporated TMS320C6457 Communications Infrastructure Digital Signal Processor www. ti. com SPRS582B--July 2010 7. 6 Reset Controller The reset controller detects the different type of resets supported on the TMS320C6457 device and manages the distribution of those resets throughout the device. The C6457 device has several types of resets: · Power-on reset · Warm reset · System reset · CPU reset Table 7-14 explains further the types of reset, the reset initiator, and the effects of each reset on the device. For more information on the effects of each reset on the PLL controllers and their clocks, see Section 7. 6. 7 ``Reset Electrical Data/Timing'' on page 128. Table 7-14 Type Power-on Reset Reset Types Initiator POR pin Effect(s) Resets the entire chip including the test and emulation logic. DDR2 memory contents will be preserved if the user places the DDR2 SDRAM in "Self-Refresh" mode before starting a Warm Reset sequence. System reset, by default, behaves as hard reset, but can be configured as soft reset if initiated by Serial RapidIO or PLLCTL. [. . . ] In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. [. . . ]