User manual TEXAS INSTRUMENTS TMS320C6672 DATA MANUAL 11-2010

[. . . ] TMS320C6672 Multicore Fixed and Floating-Point Digital Signal Processor Data Manual ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. Literature Number: SPRS708 November 2010 TMS320C6672 Data Manual SPRS708--November 2010 www. ti. com Release History Release 1. 0 Date November 2010 Chapter/Topic All Description/Comments Initial Release 2 Release History Copyright 2010 Texas Instruments Incorporated TMS320C6672 Multicore Fixed and Floating-Point Digital Signal Processor www. ti. com SPRS708--November 2010 Contents 1 Features . . 85 Copyright 2010 Texas Instruments Incorporated Contents 3 TMS320C6672 Multicore Fixed and Floating-Point Digital Signal Processor SPRS708--November 2010 5. 3 5. 4 5. 5 5. 6 5. 7 www. ti. com Bandwidth Management . 216 7. 8. 4 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing . [. . . ] · Once device initialization and the efuse farm scan are complete, the RESETSTAT signal is driven high. End Device Initialization Phase t7 t8 End of Table 7-5 ADVANCE INFORMATION 7. 3. 1. 2. 2 IO-Before-Core Power Sequencing The timing diagram for core-before-IO power sequencing is shown in Figure 7-8 and defined in Table 7-6. Figure 7-8 RESETFULL-Controlled Device Initialization -- IO Before Core Pow er Stabilization Phase POR z C hip Initialization Phase t7 R ESETFULLz RESET z C VD D(core AVS) t2b CVDD1 (core constant) t2a t3a t5 t6 DVDD18 (1. 8V) t1 DVDD15 (1. 5V) t3b REFC LKP&N t4 t3c t8 D DRC LKP&N RESET STATz RESETFULLz Controlled Reset Sequencing ­ IO before Core 102 TMS320C6672 Peripheral Information and Electrical Specifications Copyright 2010 Texas Instruments Incorporated TMS320C6672 Multicore Fixed and Floating-Point Digital Signal Processor www. ti. com SPRS708--November 2010 RESETFULL-Controlled Device Initialization -- IO Before Core System State Begin Power Stabilization Phase · DVDD18 (1. 8 V) supply is ramped up followed coincidentally by HHV (1. 8 V). · Because POR is low, all the core logic that has async reset (created from POR) is put into the reset state once the core supply ramps. · Filtered versions of 1. 8V can ramp simultaneously with DVDD18. · All input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or bidirectional pin before DVDD18 could cause damage to the device. · RESET may be driven high anytime after DVDD18 is at a valid level. In a RESETFULL-controlled boot both POR and RESET must be high before RESETFULL is driven high. Although ramping CVDD1 and CVDD simultaneously is permitted the voltage for CVDD1 must never exceed CVDD until after CVDD has reached a valid voltage. The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 (core constant) should trail CVDD (core AVS) as this will ensure that the WLs in the memories are turned off and there is no current through the memory bit cells. If, however, CVDD1 (core constant) ramps up before CVDD (core AVS) then the worst case current could be on the order of twice the specified draw of CVDD1. Although the clock inputs are not necessary at this time, they should either be driven with a valid clock or held is a static state with one leg high and one leg low. · The DDRCLK and REFCLK may begin to toggle anytime between when CVDD is at a valid level and the setup time before POR goes high specified by t7. · POR must continue to remain low for at least 100 s after power has stabilized. End Power Stabilization Phase Begin Device Initialization · Device initialization requires 500 REFCLK periods after the Power Stabilization Phase. The maximum clock period is 33. 33 nsec so a delay of an additional 16 s is required before a rising edge of POR. · RESETFULL is held low for some period after POR has transitioned high. · The rising edge of the RESETFULL will remove the reset to the efuse farm allowing the scan to begin. · The rising edge of the RESETFULL will remove the reset to the efuse farm allowing the scan to begin. · Once device initialization and the efuse farm scan are complete the RESETSTAT signal is driven high. End Device Initialization Phase Table 7-6 Time t1 t2a t2b t3a t3b t3c t4 t5 t6 t7 t8 End of Table 7-6 7. 3. 1. 3 Prolonged Resets Holding the device in POR, RESETFULL, or RESET for long periods of time will affect the long term reliability of the part. [. . . ] In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. [. . . ]