User manual TEXAS INSTRUMENTS TMS320DM365 FEATURES 11-2010

[. . . ] TMS320DM365 www. ti. com SPRS457D ­ MARCH 2009 ­ REVISED NOVEMBER 2010 TMS320DM365 Digital Media System-on-Chip (DMSoC) Check for Samples: TMS320DM365 1 TMS320DM365 Digital Media System-on-Chip (DMSoC) 1. 1 12 Features ­ DSP Instruction Extensions and Single Cycle MAC ­ ARM® Jazelle® Technology ­ Embedded ICE-RT Logic for Real-Time Debug · ARM9 Memory Architecture ­ 16K-Byte Instruction Cache ­ 8K-Byte Data Cache ­ 32K-Byte RAM ­ 16K-Byte ROM ­ Little Endian · Two Video Image Co-processors (HDVICP, MJCP) Engines ­ Support a Range of Encode and Decode Operations ­ H. 264, MPEG4, MPEG2, MJPEG, JPEG, WMV9/VC1 · Video Processing Subsystem ­ Front End Provides: · HW Face Detect Engine · Hardware IPIPE for Real-Time Image Processing ­ Resize Engine ­ Resize Images From 1/16x to 8x ­ Separate Horizontal/Vertical Control ­ Two Simultaneous Output Paths · IPIPE Interface (IPIPEIF) · Image Sensor Interface (ISIF) and CMOS Imager Interface · 16-Bit Parallel AFE (Analog Front End) Interface Up to 120 MHz · Glueless Interface to Common Video Decoders · BT. 601/BT. 656/BT. 1120 Digital YCbCr 4:2:2 (8-/16-Bit) Interface · Histogram Module · Lens distortion correction module (LDC) · Hardware 3A statistics collection module (H3A) ­ Back End Provides: · Highlights ­ High-Performance Digital Media System-on-Chip (DMSoC) ­ Up to 300-MHz ARM926EJ-S Clock Rate ­ Two Video Image Co-processors (HDVICP, MJCP) Engines ­ Supports a Range of Encode, Decode, and Video Quality Operations ­ Video Processing Subsystem · HW Face Detect Engine · Resize Engine from 1/16x to 8x · 16-Bit Parallel AFE (Analog Front-End) Interface Up to 120 MHz · 4:2:2 (8-/16-bit) Interface · 8-/16-bit YCC and Up to 24-Bit RGB888 Digital Output · 3 DACs for HD Analog Video Output · Hardware On-Screen Display (OSD) ­ Capable of 720p 30fps H. 264 video processing ­ Peripherals include EMAC, USB 2. 0 OTG, DDR2/NAND, 5 SPIs, 2 UARTs, 2 MMC/SD/SDIO, Key Scan ­ 8 Different Boot Modes and Configurable Power-Saving Modes ­ Pin-to-pin and software compatible with DM368 ­ Extended temperature (-40ºC ­ 85ºC) available for 300-Mhz device ­ 3. 3-V and 1. 8-V I/O, 1. 2-V/1. 35-V Core ­ 338-Pin Ball Grid Array at 65nm Process Technology · High-Performance Digital Media System-on-Chip (DMSoC) ­ 216-, 270-, 300-MHz ARM926EJ-S Clock Rate ­ Fully Software-Compatible With ARM9TM ­ Extended temperature available for 300-Mhz device · ARM926EJ-STM Core ­ Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2009­2010, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TMS320DM365 SPRS457D ­ MARCH 2009 ­ REVISED NOVEMBER 2010 www. ti. com · · · · · · · · · · · Hardware On-Screen Display (OSD) Composite NTSC/PAL video encoder output · 8-/16-bit YCC and Up to 24-Bit RGB888 Digital Output · 3 DACs for HD Analog Video Output · LCD Controller · BT. 601/BT. 656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface Analog-to-Digital Convertor (ADC) Power Management and Real Time Clock Subsystem (PRTCSS) ­ Real Time Clock 16-Bit Host-Port Interface (HPI) 10/100 Mb/s Ethernet Media Access Controller (EMAC) - Digital Media ­ IEEE 802. 3 Compliant ­ Supports Media Independent Interface (MII) ­ Management Data I/O (MDIO) Module Key Scan Voice Codec External Memory Interfaces (EMIFs) ­ DDR2 and mDDR SDRAM 16-bit wide EMIF With 256 MByte Address Space (1. 8-V I/O) ­ Asynchronous16-/8-bit Wide EMIF (AEMIF) · Flash Memory Interfaces ­ NAND (8-/16-bit Wide Data) ­ 16 MB NOR Flash, SRAM ­ OneNAND(16-bit Wide Data) Flash Card Interfaces ­ Two Multimedia Card (MMC) / Secure Digital (SD/SDIO) ­ SmartMedia/xD Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels) USB Port with Integrated 2. 0 High-Speed PHY that Supports ­ USB 2. 0 High-Speed Device ­ USB 2. 0 High-Speed Host (mini-host, supporting one external device) ­ USB On The Go (HS-USB OTG) Four 64-Bit General-Purpose Timers (each configurable as two 32-bit timers) · · · One 64-Bit Watch Dog Timer · Two UARTs (One fast UART with RTS and CTS Flow Control) · Five Serial Port Interfaces (SPI) each with two Chip-Selects · One Master/Slave Inter-Integrated Circuit (I2C) BusTM · One Multi-Channel Buffered Serial Port (McBSP) ­ I2S ­ AC97 Audio Codec Interface ­ S/PDIF via Software ­ Standard Voice Codec Interface (AIC12) ­ SPI Protocol (Master Mode Only) ­ Direct Interface to T1/E1 Framers ­ Time Division Multiplexed Mode (TDM) ­ 128 Channel Mode · Four Pulse Width Modulator (PWM) Outputs · Four RTO (Real Time Out) Outputs · Up to 104 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions) · Boot Modes ­ On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, UART, USB, SPI, EMAC, or HPI ­ AEMIF (NOR and OneNAND) · Configurable Power-Saving Modes · Crystal or External Clock Input (typically 19. 2 Mhz, 24 MHz, 27 Mhz or 36 MHz) · Flexible PLL Clock Generators · Debug Interface Support ­ IEEE-1149. 1 (JTAGTM) Boundary-Scan-Compatible ­ ETB (Embedded Trace Buffer) with 4K-Bytes Trace Buffer memory ­ Device Revision ID Readable by ARM · 338-Pin Ball Grid Array (BGA) Package (ZCE Suffix), 0. 65-mm Ball Pitch · 65nm Process Technology · 3. 3-V and 1. 8-V I/O, 1. 2-V/ 1. 35-V Internal · Community Resources ­ TI E2E Community ­ TI Embedded Processors Wiki 2 TMS320DM365 Digital Media System-on-Chip (DMSoC) Copyright © 2009­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 www. ti. com SPRS457D ­ MARCH 2009 ­ REVISED NOVEMBER 2010 1. 2 Description Developers can now deliver pixel-perfect images at up to 720p H. 264 at 30fps in their digital video designs without concerns of video format support, constrained network bandwidth, limited system storage capacity or cost with the new TMS320DM365 digital media processor based on DaVinci technology from Texas Instruments Incorporated (TI). [. . . ] Timing Requirements for RTCXI (1) (2) (see Figure 6-6) DEVICE MIN TYP 30. 5175 . 45C . 45C . 55C . 55C MAX µs ns ns UNIT NO. 1 2 3 (1) (2) tc(RTCXI) tw(RTCXIH) tw(RTCXIL) Cycle time, RTCXI Pulse duration, RTCXI high Pulse duration, RTCXI low The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. For example, when MXI1/CLKIN1 frequency is 24 MHz use C = 41. 6 ns. 1 2 RTCXI 3 Figure 6-10. RTCXI Timing 84 Peripheral Information and Electrical Specifications Copyright © 2009­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 www. ti. com SPRS457D ­ MARCH 2009 ­ REVISED NOVEMBER 2010 Table 6-8. Switching Characteristics Over Recommended Operating Conditions for RTC Oscillator PARAMETER Start-up time (from power up until oscillating at stable frequency) Oscillation frequency Crystal ESR Frequency stability MIN TYP 0. 85 32. 768 70 +/- 50 MAX 2 UNIT s kHz k ppm The load capacitors, C1 and C2, should be chosen such that the equation is satisfied (typical values are C1 = C2 = 2 fF). All discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator pins (RTCXI and RTCXO) and to the VSS_MX1 pin. 6. 7 Power Management and Real Time Clock Subsystem (PRTCSS) The Power Management and Real Time Clock Subsystem (PRTCSS) is used for calendar applications. The PRTCSS has an independent power supply and can remain ON while the rest of the power supply is turned OFF. The PRTCSS supports the following features: · Real Time Clock (RTC) ­ Simple day counter (Up to 89-years) ­ To generate the Alarm event to check the RTC count ­ 16-bit simple timer ­ Watch-dog timer to generate the event for RTC-Sequencer · General Purpose I/O with Anti-chattering ­ 3-output pins (PWRCTRO[2:0]) ­ 7-In/Output pins (PWRCTRIO[6:0]) · Interrupt ­ 2 RTCSS interrupts (ARMSS and Timer) ­ 7 GPIO interrupts (PWRCTRIO[6:0] 6. 7. 1 PRTCSS Peripheral Register Description(s) The following table lists the PRTCSS Interface registers (PRTCIF) and Table 6-10 lists the PRTCSS registers which can only be accessed via the PRTCIF registers, their corresponding acronyms, and device memory locations (offsets). For more details, see the TMS320DM36x PRTCSS User's Guide (literature number SPRUFJ0). PRTC Interface (PRTCIF) Registers Offset 0x0 0x4 0x8 0xC 0x10 0x14 Acronym PID PRTCIF_CTRL PRTCIF_LDATA PRTCIF_UDATA PRTCIF_INTEN PRTCIF_INTFLG Register Description PRTCIF peripheral ID register PRTCIF control register PRTCIF access lower data register PRTCIF access upper data register PRTCIF interrupt enable register PRTCIF interrupt flag register Table 6-10. Power Management and Real Time Clock Subsystem (PRTCSS) Registers Offset 0x0 0x1 0x2 0x3 Acronym GO_OUT GIO_OUT GIO_DIR GIO_IN Register Description Global output pin output data register Global input/output pin output data register Global input/output pin direction register Global input/output pin input data register Copyright © 2009­2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM365 85 TMS320DM365 SPRS457D ­ MARCH 2009 ­ REVISED NOVEMBER 2010 www. ti. com Table 6-10. Power Management and Real Time Clock Subsystem (PRTCSS) Registers (continued) Offset 0x4 0x5 0x6 0x7 0x8 0x9 - 0xA 0xB 0xC 0xD 0xE 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x20 Acronym GIO_FUNC GIO_RISE_INT_EN GIO_FALL_INT_EN GIO_RISE_INT_FLG GIO_FALL_INT_FLG Reserved INTC_EXTENA0 INTC_EXTENA1 INTC_FLG0 INTC_FLG1 RTC_CTRL RTC_WDT RTC_TMR0 RTC_TMR1 RTC_CCTRL RTC_SEC RTC_MIN RTC_HOUR RTC_DAY0 RTC_DAY1 RTC_AMIN RTC_AHOUR RTC_ADAY0 RTC_ADAY1 CLKC_CNT Register Description Global input/output pin function register GIO rise interrupt enable register GIO fall interrupt enable register GIO rise interrupt flag register GIO fall interrupt flag register Reserved EXT interrupt enable 0 register EXT interrupt enable 1 register Event interrupt flag 0 register Event interrupt flag 1 register RTC control register Watchdog timer counter register Timer counter 0 register Timer counter 1 register Calender control register Seconds register Minutes register Hours register Days[[7:0] register Days[14:8] register Minutes Alarm register Hour Alarm register Days[7:0] Alarm register Days[14:8] Alarm register Clock control register 86 Peripheral Information and Electrical Specifications Copyright © 2009­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM365 TMS320DM365 www. ti. com SPRS457D ­ MARCH 2009 ­ REVISED NOVEMBER 2010 6. 8 General-Purpose Input/Output (GPIO) The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs. When configured as an output, a write to an internal register can control the state driven on the output pin. When configured as an input, the state of the input is detectable by reading the state of an internal register. In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different interrupt/event generation modes. The GPIO pins are grouped into banks of 16 pins per bank (i. e. , bank 0 consists of GPIO [0:15]). There are a total of 7 GPIO banks in the device, because the device has 104 GPIOs. For additional details on GPIO pins voltage level and the associated power supply please see Table 6-11. GPIO Pin Voltage Level and Power Supply Reference Voltage Level Power Supply Name Pin Name VDD_AEMIF1_18_33 GIO[78:68] GIO[66:56] GIO[51:50] 1. 8 V or 3. 3 V VDD_AEMIF2_18_33 GIO[67] GIO[55:52] VDD_ISIF18_33 GIO[103:93] 3. 3 V VDDS33 GIO[92:79] GIO[49:0] 1. 8 V VDD18_PRTCSS GIO[110:104] The GPIO peripheral supports the following: · Up to 104 GPIO pins, GPIO[103:0] · Up to 7 GPIO pins dedicated to the PRTC Subsystem. Only PWRCTRIO[2:0] are connected to the GPIO module, labeled as GPIO[106:104]. For the PRTCSS module the PWRCTRIO[6:0] pins support input and output functionality but for the GPIO module the GPIO[106:104] pins support input functionality only. · Interrupts: ­ Up to 15 unique GPIO[15:0] interrupts from Bank 0. [. . . ] In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE OPTION ADDENDUM www. ti. com 23-Oct-2010 Addendum-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. [. . . ]