User manual TEXAS INSTRUMENTS TMS320DM641 DATA MANUAL 10-2010

[. . . ] TMS320DM641/TMS320DM640 Video/Imaging Fixed-Point Digital Signal Processors Data Manual Literature Number: SPRS222F June 2003 - Revised October 2010 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. This page intentionally left blank Revision History Revision History This data sheet revision history highlights the technical changes made to the SPRS222E device-specific data sheet to make it an SPRS222F revision. PAGE(s) NO. 82 Added note for VOH and VOL. ADDS/CHANGES/DELETES June 2003 - Revised October 2010 SPRS222F 3 Contents Contents Section 1 Page 15 15 16 18 20 20 22 25 28 30 31 32 32 36 42 64 64 65 65 66 67 68 68 68 69 69 69 72 74 76 77 77 82 82 82 83 84 84 84 84 84 Device Overview . [. . . ] For more detailed information on the peripheral configuration pins and the PERCFG register bits, see the Device Configurations section of this document. 4. 3. 5 Power-Down Modes Logic Figure 4-8 shows the power-down mode logic on the DM641/DM640. CLKOUT4 CLKOUT6 Internal Clock Tree Clock Distribution and Dividers PD1 PD2 Clock PLL PowerDown Logic IFR IER PWRD CSR CPU Internal Peripherals PD3 TMS320DM641/DM640 CLKIN RESET External input clocks, with the exception of CLKIN, are not gated by the power-down mode logic. Figure 4-8. Power-Down Mode Logic June 2003 - Revised October 2010 SPRS222F 87 Power Supplies 4. 3. 6 Triggering, Wake-up, and Effects The power-down modes and their wake-up methods are programmed by setting the PWRD field (bits 15-10) of the control status register (CSR). The PWRD field of the CSR is shown in Figure 4-9 and described in Table 4-2. When writing to the CSR, all bits of the PWRD field should be set at the same time. Logic 0 should be used when writing to the reserved bit (bit 15) of the PWRD field. The CSR is discussed in detail in the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189). 31 16 15 Reserved R/W-0 7 14 Enable or Non-Enabled Interrupt Wake R/W-0 13 Enabled Interrupt Wake R/W-0 12 PD3 R/W-0 11 PD2 R/W-0 10 PD1 R/W-0 9 8 0 Legend: R/W-x = Read/write reset value NOTE: The shadowed bits are not part of the power-down logic discussion and therefore are not covered here. For information on these other bit fields in the CSR register, see the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189). Figure 4-9. PWRD Field of the CSR Register A delay of up to nine clock cycles may occur after the instruction that sets the PWRD bits in the CSR before the PD mode takes effect. As best practice, NOPs should be padded after the PWRD bits are set in the CSR to account for this delay. If PD1 mode is terminated by a non-enabled interrupt, the program execution returns to the instruction where PD1 took effect. If PD1 mode is terminated by an enabled interrupt, the interrupt service routine will be executed first, then the program execution returns to the instruction where PD1 took effect. In the case with an enabled interrupt, the GIE bit in the CSR and the NMIE bit in the interrupt enable register (IER) must also be set in order for the interrupt service routine to execute; otherwise, execution returns to the instruction where PD1 took effect upon PD1 mode termination by an enabled interrupt. Table 4-2 summarizes all the power-down modes. 88 SPRS222F June 2003 - Revised October 2010 Enhanced Direct Memory Access (EDMA) Controller Table 4-2. Characteristics of the Power-Down Modes PRWD FIELD (BITS 15-10) 000000 001001 010001 POWER-DOWN MODE No power-down PD1 PD1 WAKE-UP METHOD -- Wake by an enabled interrupt Wake by an enabled or non-enabled interrupt EFFECT ON CHIP'S OPERATION -- CPU halted (except for the interrupt logic) Power-down mode blocks the internal clock inputs at the boundary of the CPU, preventing most of the CPU's logic from switching. During PD1, EDMA transactions can proceed between peripherals and internal memory. Output clock from PLL is halted, stopping the internal clock structure from switching and resulting in the entire chip being halted. All functional I/O "freeze" in the last state when the PLL clock is turned off. All functional I/O "freeze" in the last state when the PLL clock is turned off. Following reset, the PLL needs time to re-lock, just as it does following power-up. Wake-up from PD3 takes longer than wake-up from PD2 because the PLL needs to be re-locked, just as it does following power-up. -- 011010 PD2 Wake by a device reset 011100 PD3 Wake by a device reset All others Reserved -- When entering PD2 and PD3, all functional I/O remains in the previous state. [. . . ] Substrate color may vary. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. [. . . ]