User manual TEXAS INSTRUMENTS TMS320DM6441 DATASHEET 08-2010

[. . . ] TMS320DM6441 www. ti. com SPRS359E ­ SEPTEMBER 2006 ­ REVISED AUGUST 2010 TMS320DM6441 Digital Media System-on-Chip Check for Samples: TMS320DM6441 1 Digital Media System-on-Chip (DMSoC) 1. 1 12 Features · C64x+ L1/L2 Memory Architecture ­ 32K-Byte L1P Program RAM/Cache (Direct Mapped) ­ 80K-Byte L1D Data RAM/Cache (2-Way Set-Associative) ­ 64K-Byte L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation) · ARM926EJ-S Core ­ Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets ­ DSP Instruction Extensions and Single Cycle MAC ­ ARM® Jazelle® Technology ­ Embedded ICE-RTTM Logic for Real-Time Debug · ARM9 Memory Architecture ­ 16K-Byte Instruction Cache ­ 8K-Byte Data Cache ­ 16K-Byte RAM ­ 8K-Byte ROM · Embedded Trace BufferTM (ETB11TM) With 4KB Memory for ARM9 Debug · Endianness: Little Endian for ARM and DSP · Video Imaging Co-Processor (VICP) · Video Processing Subsystem ­ Front End Provides: · CCD and CMOS Imager Interface · BT. 601/BT. 656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface · Preview Engine for Real-Time Image Processing · Glueless Interface to Common Video Decoders · Histogram Module · Auto-Exposure, Auto-White Balance, and Auto-Focus Module · Resize Engine ­ Resize Images From 1/4x to 4x ­ Separate Horizontal/Vertical Control · High-Performance Digital Media SoC ­ C64x+TM DSP Clock Rate · 405-MHz (Max) at 1. 05 V or 513-MHz (Max) at 1. 2 V ­ ARM926EJ-STM Clock Rate · 202. 5-MHz (Max) at 1. 05 V or 256-MHz (Max) at 1. 2 V ­ Eight 32-Bit C64x+ Instructions/Cycle ­ 4752 C64x+ MIPS ­ Fully Software-Compatible With C64x / ARM9TM · Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+TM DSP Core ­ Eight Highly Independent Functional Units · Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle · Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle ­ Load-Store Architecture With Non-Aligned Support ­ 64 32-Bit General-Purpose Registers ­ Instruction Packing Reduces Code Size ­ All Instructions Conditional ­ Additional C64x+TM Enhancements · Protected Mode Operation · Exceptions Support for Error Detection and Program Redirection · Hardware Support for Modulo Loop Operation · C64x+ Instruction Set Features ­ Byte-Addressable (8-/16-/32-/64-Bit Data) ­ 8-Bit Overflow Protection ­ Bit-Field Extract, Set, Clear ­ Normalization, Saturation, Bit-Counting ­ Compact 16-Bit Instructions ­ Additional Instructions to Support Complex Multiplies 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2006­2010, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TMS320DM6441 SPRS359E ­ SEPTEMBER 2006 ­ REVISED AUGUST 2010 www. ti. com · Video Processing Subsystem (Continued) ­ Back End Provides: · Hardware On-Screen Display (OSD) · Four 54-MHz DACs for a Combination of ­ Composite NTSC/PAL Video ­ Luma/Chroma Separate Video (S-video) ­ Component (YPbPr or RGB) Video (Progressive) · Digital Output ­ 8-/16-bit YUV or up to 24-Bit RGB ­ HD Resolution ­ Up to Two Video Windows · External Memory Interfaces (EMIFs) ­ 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1. 8-V I/O) ­ Asynchronous16-Bit-Wide EMIF (EMIFA) With 128M-Byte Address Reach · Flash Memory Interfaces ­ NOR (8-/16-Bit-Wide Data) ­ NAND (8-/16-Bit-Wide Data) · Flash Card Interfaces ­ Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO) ­ CompactFlash Controller With True IDE Mode ­ SmartMedia ­ Memory Stick® and Memory Stick PROTM · Enhanced Direct-Memory-Access (EDMA3) Controller (64 Independent Channels) · Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers) · One 64-Bit Watch Dog Timer · Three UARTs (One with RTS and CTS Flow Control) · One Serial Port Interface (SPI) With Two Chip-Selects · Master/Slave Inter-Integrated Circuit (I2C BusTM) · Audio Serial Port (ASP) ­ I2S ­ AC97 Audio Codec Interface ­ Standard Voice Codec Interface (AIC12) · 10/100 Mb/s Ethernet MAC (EMAC) ­ IEEE 802. 3 Compliant ­ Media Independent Interface (MII) · VLYNQTM Interface (FPGA Interface) · Host Port Interface (HPI) with 16-Bit Multiplexed Address/Data · USB Port With Integrated 2. 0 PHY ­ USB 2. 0 High-/Full-Speed Client ­ USB 2. 0 High-/Full-/Low-Speed Host · Three Pulse Width Modulator (PWM) Outputs · On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash or UART · ATA/ATAPI I/F (ATA/ATAPI-5 Specification) · Individual Power-Saving Modes for ARM/DSP · Flexible PLL Clock Generators · IEEE-1149. 1 (JTAG) BoundaryScan-Compatible · Up to 71 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions) · 361-Pin Pb-Free BGA Package (ZWT Suffix), 0. 8-mm Ball Pitch · 0. 09-µm/6-Level Cu Metal Process (CMOS) · 3. 3-V and 1. 8-V I/O, 1. 05-V or 1. 2-V internal · Applications: ­ Digital Media ­ Networked Media Encode/Decode ­ Video Imaging ­ Portable Media Players 2 Digital Media System-on-Chip (DMSoC) Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 Copyright © 2006­2010, Texas Instruments Incorporated TMS320DM6441 www. ti. com SPRS359E ­ SEPTEMBER 2006 ­ REVISED AUGUST 2010 1. 2 Description The TMS320DM6441 (also referenced as DM6441) leverages TI's DaVinciTM technology to meet the networked media encode and decode application processing needs of next-generation embedded devices. [. . . ] NOTE The DVDDXX supply power-up is specified relative to the CVDD supply power-up, not the CVDDDSP supply. Table 6-2. 1 td(CVDD-DVDD) Delay time, CVDD supply ready to DVDDXX supply ramp start 1. 05 V and 1. 2 V MIN 0 MAX 100 ms UNIT CVDD 1 DVDDXX (A) Note A: DVDDXX denotes all I/O supplies. Figure 6-5. I/O Supply Timings There is not a specific power-up sequence that must be followed with respect to the order of the power-up of the DVDD18, DVDDR2, and DVDD33 supplies. Once the CVDD supply is powered up and the td(CVDD-DVDDXX) specification is met, the DVDD18, DVDDR2, and DVDD33 supplies may be powered up in any order of preference. All other supplies may also be powered up in any order of preference once the td(CVDD-DVDDXX) specification has been met. Copyright © 2006­2010, Texas Instruments Incorporated Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 95 TMS320DM6441 SPRS359E ­ SEPTEMBER 2006 ­ REVISED AUGUST 2010 www. ti. com 6. 3. 1. 1 Power-Supply Design Considerations Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize inductance and resistance in the power delivery path. Additionally, when designing for high-performance applications utilizing the DM6441 device, the PC board should include separate power planes for core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors. 6. 3. 1. 2 Power-Supply Decoupling In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as possible close to DM6441. Assuming 0603 caps, the user should be able to fit a total of 60 caps, 30 for the core supplies and 30 for the I/O supplies. These caps need to be close to the DM6441 power pins, no more than 1. 25 cm maximum distance to be effective. Physically smaller caps, such as 0402, are better because of their lower parasitic inductance. Medium bypass caps (220 nF or as large as can be obtained in a small package) should be next closest. TI recommends no less than eight small and eight medium caps per supply be placed immediately next to the BGA vias, using the "interior" BGA space and at least the corners of the "exterior". Larger caps for each supply can be placed further away for bulk decoupling. Large bulk caps (on the order of 100 mF) should be furthest away, but still as close as possible. Large caps for each supply should be placed outside of the BGA footprint. Any cap selection needs to be evaluated from a yield/manufacturing point-of-view. As with the selection of any component, verification of capacitor availability over the product's production lifetime should be considered. 6. 3. 1. 3 DM6441 Power and Clock Domains DM6441 includes two separate power domains: "Always On" and "DSP". The "Always On" power domain is always on when the chip is on. The "Always On" domain is powered by the VDD pins of the DM6441. The majority of the DM6441's modules lie within the "Always On" power domain. A separate domain called the "DSP" domain houses the C64x+ and VICP. [. . . ] In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. [. . . ]