User manual TEXAS INSTRUMENTS TMS320DM6443 DATASHEET 08-2010

[. . . ] TMS320DM6443 www. ti. com SPRS282G ­ DECEMBER 2005 ­ REVISED AUGUST 2010 TMS320DM6443 Digital Media System-on-Chip Check for Samples: TMS320DM6443 1 Digital Media System-on-Chip (DMSoC) 1. 1 12 Features · C64x+ L1/L2 Memory Architecture ­ 32K-Byte L1P Program RAM/Cache (Direct Mapped) ­ 80K-Byte L1D Data RAM/Cache (2-Way Set-Associative) ­ 64K-Byte L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation) · ARM926EJ-S Core ­ Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets ­ DSP Instruction Extensions and Single Cycle MAC ­ ARM® Jazelle® Technology ­ EmbeddedICE-RTTM Logic for Real-Time Debug · ARM9 Memory Architecture ­ 16K-Byte Instruction Cache ­ 8K-Byte Data Cache ­ 16K-Byte RAM ­ 8K-Byte ROM · Emulation Trace BufferTM (ETB11TM) With 4-KB Memory for ARM9 Debug · Endianness: Little Endian for ARM and DSP · Video Processing Subsystem ­ Resize Engine Provides: · Resize Images From 1/4x to 4x · Separate Horizontal and Vertical Control ­ Back End Provides: · Hardware On-Screen Display (OSD) · 4 - 54 MHz DACs for a Combination of ­ Composite NTSC/PAL Video ­ Luma/Chroma Separate Video (S-video) ­ Component (YPbPr or RGB) Video (Progressive) · Digital Output ­ 8-/16-Bit YUV or up to 24-Bit RGB ­ HD Resolution ­ Up to 2 Video Windows · High-Performance Digital Media SoC ­ 594-MHz C64x+TM Clock Rate ­ 297-MHz ARM926EJ-STM Clock Rate ­ Eight 32-Bit C64x+ Instructions/Cycle ­ 4752 C64x+ MIPS ­ Fully Software-Compatible With C64x / ARM9TM · Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+TM DSP Core ­ Eight Highly Independent Functional Units · Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle · Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle ­ Load-Store Architecture With Non-Aligned Support ­ 64 32-Bit General-Purpose Registers ­ Instruction Packing Reduces Code Size ­ All Instructions Conditional ­ Additional C64x+TM Enhancements · Protected Mode Operation · Exceptions Support for Error Detection and Program Redirection · Hardware Support for Modulo Loop Operation · C64x+ Instruction Set Features ­ Byte-Addressable (8-/16-/32-/64-Bit Data) ­ 8-Bit Overflow Protection ­ Bit-Field Extract, Set, Clear ­ Normalization, Saturation, Bit-Counting ­ Compact 16-Bit Instructions ­ Additional Instructions to Support Complex Multiplies 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2005­2010, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TMS320DM6443 SPRS282G ­ DECEMBER 2005 ­ REVISED AUGUST 2010 www. ti. com · External Memory Interfaces (EMIFs) ­ 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1. 8-V I/O) ­ Asynchronous16-Bit-Wide EMIF (EMIFA) With 128M-Byte Address Reach · Flash Memory Interfaces ­ NOR (8-/16-Bit-Wide Data) ­ NAND (8-/16-Bit-Wide Data) · Flash Card Interfaces ­ Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO) ­ Compact Flash Controller With True IDE Mode ­ SmartMedia · Enhanced Direct-Memory-Access (EDMA3) Controller (64 Independent Channels) · Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers) · One 64-Bit Watch Dog Timer · Three UARTs (One with RTS and CTS Flow Control) · One Serial Peripheral Interface (SPI) with Two Chip-Selects · Master/Slave Inter-Integrated Circuit (I2C BusTM) · Audio Serial Port (ASP) ­ I2S ­ AC97 Audio Codec Interface ­ Standard Voice Codec Interface (AIC12) · 10/100 Mb/s Ethernet MAC (EMAC) ­ IEEE 802. 3 Compliant ­ Media Independent Interface (MII) · VLYNQTM Interface (FPGA Interface) · Host-Port Interface (HPI) with 16-Bit Multiplexed Address/Data · USB Port With Integrated 2. 0 PHY ­ USB 2. 0 High-/Full-Speed (480 Mbps) Client ­ USB 2. 0 High-/Full-/Low-Speed Host (Mini-Host, Supporting One External Device) · Three Pulse Width Modulator (PWM) Outputs · On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash or UART · ATA/ATAPI I/F (ATA/ATAPI-6 Specification) · Individual Power-Saving Modes for ARM/DSP · Flexible PLL Clock Generators · IEEE-1149. 1 (JTAG) BoundaryScan-Compatible · Up to 71 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions) · 361-Pin Pb-Free BGA Package (ZWT Suffix), 0. 8-mm Ball Pitch · 0. 09-mm/6-Level Cu Metal Process (CMOS) · 3. 3-V and 1. 8-V I/O, 1. 2-V Internal · Applications: ­ Digital Media ­ Networked Media Encode/Decode ­ Video Imaging 2 Digital Media System-on-Chip (DMSoC) Submit Documentation Feedback Product Folder Link(s): TMS320DM6443 Copyright © 2005­2010, Texas Instruments Incorporated TMS320DM6443 www. ti. com SPRS282G ­ DECEMBER 2005 ­ REVISED AUGUST 2010 1. 2 Description The TMS320DM6443 (also referenced as DM6443) leverages TI's DaVinciTM technology to meet the networked media encode and decode application processing needs of next-generation embedded devices. [. . . ] For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data manual timings. Input requirements in this data manual are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin. Figure 6-1. Test Load Circuit for AC Timing Measurements The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving. 6. 1. 1. 1 Signal Transition Levels All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. Input and Output Voltage Reference Levels for AC Timing Measurements All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOLMAX and VOH MIN for output clocks. Vref = VIH MIN (or VOH MIN) Vref = VIL MAX (or VOL MAX) Figure 6-3. Rise and Fall Transition Time Voltage Reference Levels Copyright © 2005­2010, Texas Instruments Incorporated Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM6443 89 TMS320DM6443 SPRS282G ­ DECEMBER 2005 ­ REVISED AUGUST 2010 www. ti. com 6. 1. 1. 2 Timing Parameters and Board Routing Analysis The timing parameter values specified in this data manual do not include delays by board routings. As a good board design practice, such delays must always be taken into account. TI recommends utilizing the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing differences. For the DDR2 memory controller interface, it is not necessary to use the IBIS models to analyze timing characteristics. TI provides a PCB routing rules solution that describes the routing rules to ensure the DDR2 memory controller interface timings are met. See the Implementing DDR2 PCB Layout on the TMS320DM644x DSP Application Report (literature number SPRAAC5). 6. 2 Recommended Clock and Control Signal Transition Behavior All clocks and control signals should transition between VIH and VIL (or between VIL and VIH) in a monotonic manner. 6. 3 Power Supplies For more information regarding TI's power management products and suggested devices to power TI DSPs, visit www. ti. com/dsppower. 6. 3. 1 Power-Supply Sequencing The DM6443 includes two core supplies -- CVDD and CVDDDSP, as well as three I/O supplies -- DVDD18, DVDDR2, and DVDD33. To ensure proper device operation, a specific power-up sequence must be followed. The core supply power-up sequence is dependent on the DSP boot mode selected at reset. If the DSP boot mode is configured as Self-Boot mode, then both core supplies must be powered up at the same time. If the DSP boot mode is configured as Host-Boot, where the ARM boots the DSP, the two core supplies may be ramped simultaneously or powered up separately. When powered up separately, the CVDDDSP supply must not be ramped prior to the CVDD supply. The CVDDDSP supply must be powered up before the shorting switch is closed (enabled). [. . . ] In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. [. . . ]