User manual TEXAS INSTRUMENTS TMS320F28030 DATA MANUAL REV D

[. . . ] TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www. ti. com SPRS584D ­ APRIL 2009 ­ REVISED JUNE 2010 Piccolo Microcontrollers Check for Samples: TMS320F28030, TMS320F28031, TMS320F28032, TMS320F28033, TMS320F28034, TMS320F28035 1 TMS320F2803x ( PiccoloTM) MCUs 1. 1 123 Features ­ Low Power ­ No Analog Support Pins Clocking: ­ Two Internal Zero-pin Oscillators ­ On-Chip Crystal Oscillator/External Clock Input ­ Dynamic PLL Ratio Changes Supported ­ Watchdog Timer Module ­ Missing Clock Detection Circuitry Up to 45 Individually Programmable, Multiplexed GPIO Pins With Input Filtering Peripheral Interrupt Expansion (PIE) Block That Supports All Peripheral Interrupts Three 32-Bit CPU Timers Independent 16-Bit Timer in Each ePWM Module On-Chip Memory ­ Flash, SARAM, OTP, Boot ROM Available 128-Bit Security Key/Lock ­ Protects Secure Memory Blocks ­ Prevents Firmware Reverse Engineering Serial Port Peripherals ­ One SCI (UART) Module ­ Two SPI Modules ­ One Inter-Integrated-Circuit (I2C) Bus ­ One Local Interconnect Network (LIN) Bus ­ One Enhanced Controller Area Network (eCAN) Bus Advanced Emulation Features ­ Analysis and Breakpoint Functions ­ Real-Time Debug via Hardware 2803x Packages ­ 64-Pin PAG Thin Quad Flatpack (TQFP) ­ 80-Pin PN Low-Profile Quad Flatpack (LQFP) Community Resources ­ TI E2E Community ­ TI Embedded Processors Wiki · Highlights ­ High-Efficiency 32-Bit CPU ( TMS320C28xTM) ­ 60-MHz Device ­ Single 3. 3-V Supply ­ Integrated Power-on and Brown-out Resets ­ Two Internal Zero-pin Oscillators ­ Up to 45 Multiplexed GPIO Pins ­ Three 32-Bit CPU Timers ­ On-Chip Flash, SARAM, OTP Memory ­ Code-Security Module ­ Serial Port Peripherals (SCI/SPI/I2C/LIN/eCAN) ­ Enhanced Control Peripherals · Enhanced Pulse Width Modulator (ePWM) · High-Resolution PWM (HRPWM) · Enhanced Capture (eCAP) · Enhanced Quadrature Encoder Pulse (eQEP) · Analog-to-Digital Converter (ADC) · On-Chip Temperature Sensor · Comparator ­ 64-Pin and 80-Pin Packages · High-Efficiency 32-Bit CPU ( TMS320C28xTM) ­ 60 MHz (16. 67-ns Cycle Time) ­ 16 x 16 and 32 x 32 MAC Operations ­ 16 x 16 Dual MAC ­ Harvard Bus Architecture ­ Atomic Operations ­ Fast Interrupt Response and Processing ­ Unified Memory Programming Model ­ Code-Efficient (in C/C++ and Assembly) · Programmable Control Law Accelerator (CLA) ­ 32-Bit Floating-Point Math Accelerator ­ Executes Code Independently of the Main CPU · Low Device and System Cost: ­ Single 3. 3-V Supply ­ No Power Sequencing Requirement ­ Integrated Power-on Reset and Brown-out Reset 1 · · · · · · · · · · · 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Piccolo, TMS320C28x, C28x, TMS320C2000, Code Composer Studio, XDS510 are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. Copyright © 2009­2010, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. [. . . ] Analog Pin Configurations 50 Peripherals Copyright © 2009­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28030 TMS320F28031 TMS320F28032 TMS320F28033 TMS320F28034 TMS320F28035 TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www. ti. com SPRS584D ­ APRIL 2009 ­ REVISED JUNE 2010 4. 2. 1 4. 2. 1. 1 ADC Features The core of the ADC contains a single 12-bit converter fed by two sample-and-hold circuits. The sample-and-hold circuits can be sampled simultaneously or sequentially. The converter can be configured to run with an internal bandgap reference to create true-voltage based conversions or with a pair of external voltage references (VREFHI/VREFLO) to create ratiometric-based conversions. It is easy for the user to create a series of conversions from a single trigger. However, the basic principle of operation is centered around the configurations of individual conversions, called SOCs, or Start-Of-Conversions. Functions of the ADC module include: · 12-bit ADC core with built-in dual sample-and-hold (S/H) · Simultaneous sampling or sequential sampling modes · Full range analog input: 0 V to 3. 3 V fixed, or VREFHI/VREFLO ratiometric. The digital value of the input analog voltage is derived by: ­ Internal Reference Digital Value = 0, when input £ 0 V Digital Value = 4096 ´ Input Analog Voltage - ADCLO 3. 3 when 0 V < input < 3. 3 V Digital Value = 4095, when input ³ 3. 3 V when input £ 0 V Input Analog Voltage - ADCLO VREFHI - VREFLO when 0 V < input < VREFHI ­ External Reference Digital Value = 0, Digital Value = 4096 ´ Digital Value = 4095, when input ³ VREFHI · · · · · · Runs at full system clock, no prescaling required Up to 16-channel, multiplexed inputs 16 SOCs, configurable for trigger, sample window, and channel 16 result registers (individually addressable) to store conversion values Multiple trigger sources ­ S/W ­ software immediate start ­ ePWM 1­7 ­ GPIO XINT2 ­ CPU Timers 0/1/2 ­ ADCINT1/2 9 flexible PIE interrupts, can configure interrupt request after any conversion Copyright © 2009­2010, Texas Instruments Incorporated Peripherals Submit Documentation Feedback Product Folder Link(s): TMS320F28030 TMS320F28031 TMS320F28032 TMS320F28033 TMS320F28034 TMS320F28035 51 TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584D ­ APRIL 2009 ­ REVISED JUNE 2010 www. ti. com Table 4-3. ADC Configuration and Control Registers REGISTER NAME ADCCTL1 ADCINTFLG ADCINTFLGCLR ADCINTOVF ADCINTOVFCLR ADCINTSEL1AND2 ADCINTSEL3AND4 ADCINTSEL5AND6 ADCINTSEL7AND8 ADCINTSEL9AND10 ADCSOCPRIORITYCTL ADCSAMPLEMODE ADCINTSOCSEL1 ADCINTSOCSEL2 ADCSOCFLG1 ADCSOCFRC1 ADCSOCOVF1 ADCSOCOVFCLR1 ADCSOC0CTL to ADCSOC15CTL ADCREFTRIM ADCOFFTRIM ADCREV ADDRESS 0x7100 0x7104 0x7105 0x7106 0x7107 0x7108 0x7109 0x710A 0x710B 0x710C 0x7110 0x7112 0x7114 0x7115 0x7118 0x711A 0x711C 0x711E 0x7120 ­ 0x712F 0x7140 0x7141 0x714F SIZE (x16) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 EALLOW PROTECTED Yes No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No Yes Yes Yes No Control 1 Register Interrupt Flag Register Interrupt Flag Clear Register Interrupt Overflow Register Interrupt Overflow Clear Register Interrupt 1 and 2 Selection Register Interrupt 3 and 4 Selection Register Interrupt 5 and 6 Selection Register Interrupt 7 and 8 Selection Register Interrupt 9 Selection Register (reserved Interrupt 10 Selection) SOC Priority Control Register Sampling Mode Register Interrupt SOC Selection 1 Register (for 8 channels) Interrupt SOC Selection 2 Register (for 8 channels) SOC Flag 1 Register (for 16 channels) SOC Force 1 Register (for 16 channels) SOC Overflow 1 Register (for 16 channels) SOC Overflow Clear 1 Register (for 16 channels) SOC0 Control Register to SOC15 Control Register Reference Trim Register Offset Trim Register Revision Register DESCRIPTION Table 4-4. ADC Result Registers (Mapped to PF0) REGISTER NAME ADCRESULT0 to ADCRESULT15 ADDRESS 0xB00 ­ 0xB0F SIZE (x16) 1 EALLOW PROTECTED No DESCRIPTION ADC Result 0 Register to ADC Result 15 Register 52 Peripherals Copyright © 2009­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28030 TMS320F28031 TMS320F28032 TMS320F28033 TMS320F28034 TMS320F28035 TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www. ti. com SPRS584D ­ APRIL 2009 ­ REVISED JUNE 2010 0-Wait Result Registers PF0 (CPU) PF2 (CPU) SYSCLKOUT ADCENCLK ADCINT 1 PIE ADCINT 9 ADCTRIG 1 ADCTRIG 2 AIO MUX ADC Channels ADC Core 12-Bit ADCTRIG 3 ADCTRIG 4 ADCTRIG 5 ADCTRIG 6 ADCTRIG 7 ADCTRIG 8 ADCTRIG 9 ADCTRIG 10 ADCTRIG 11 ADCTRIG 12 ADCTRIG 13 ADCTRIG 14 ADCTRIG 15 ADCTRIG 16 ADCTRIG 17 ADCTRIG 18 TINT 0 TINT 1 TINT 2 XINT 2SOC SOCA 1 SOCB 1 SOCA 2 SOCB 2 SOCA 3 SOCB 3 SOCA 4 SOCB 4 SOCA 5 SOCB 5 SOCA 6 SOCB 6 SOCA 7 SOCB 7 CPUTIMER 0 CPUTIMER 1 CPUTIMER 2 XINT 2 EPWM 1 EPWM 2 EPWM 3 EPWM 4 EPWM 5 EPWM 6 EPWM 7 Figure 4-3. ADC Connections ADC Connections if the ADC is Not Used It is recommended that the connections for the analog power pins be kept, even if the ADC is not used. Following is a summary of how the ADC pins should be connected, if the ADC is not used in an application: · VDDA ­ Connect to VDDIO · VSSA ­ Connect to VSS · VREFLO ­ Connect to VSS · ADCINAn, ADCINBn ­ Connect to VSSA When the ADC module is used in an application, unused ADC input pins should be connected to analog ground (VSSA). NOTE: Unused ADCIN pins that are multiplexed with AIO function should not be directly connected to analog ground. This is to prevent an errant code from configuring these pins as AIO outputs and driving grounded pins to a logic-high state. When the ADC is not used, be sure that the clock to the ADC module is not turned on to realize power savings. Copyright © 2009­2010, Texas Instruments Incorporated Peripherals Submit Documentation Feedback Product Folder Link(s): TMS320F28030 TMS320F28031 TMS320F28032 TMS320F28033 TMS320F28034 TMS320F28035 53 TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584D ­ APRIL 2009 ­ REVISED JUNE 2010 www. ti. com 4. 2. 2 ADC MUX To COMPy A or B input To ADC Channel X AIOx Pin AIOxIN AIOxINE Logic implemented in GPIO MUX block SYSCLK 1 SYNC 0 AIODAT Reg (Latch) AIOMUX 1 Reg AIODAT Reg (Read) AIOxDIR (1 = Input, 0 = Output) AIOSET, AIOCLEAR, AIOTOGGLE Regs 1 AIODIR Reg (Latch) (0 = Input, 1 = Output) 0 0 Figure 4-4. AIOx Pin Multiplexing The ADC channel and Comparator functions are always available. The digital I/O function is available only when the respective bit in the AIOMUX1 register is 0. In this mode, reading the AIODAT register reflects the actual pin state. The digital I/O function is disabled when the respective bit in the AIOMUX1 register is 1. In this mode, reading the AIODAT register reflects the output latch of the AIODAT register and the input digital I/O buffer is disabled to prevent analog signals from generating noise. If the pin is used as an analog input, users should keep the AIO function disabled for that pin. 54 Peripherals Copyright © 2009­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28030 TMS320F28031 TMS320F28032 TMS320F28033 TMS320F28034 TMS320F28035 TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www. ti. com SPRS584D ­ APRIL 2009 ­ REVISED JUNE 2010 4. 2. 3 Comparator Block Figure 4-5 shows the interaction of the Comparator modules with the rest of the system. COMP x A COMP x B + COMP COMP x + DAC x Wrapper COMPxOUT DAC Core 10-Bit GPIO MUX TZ1/2/3 AIO MUX ePWM Figure 4-5. Comparator Control Registers REGISTER NAME COMPCTL COMPSTS DACVAL COMP1 ADDRESS 0x6400 0x6402 0x6406 COMP2 ADDRESS 0x6420 0x6422 0x6426 COMP3 ADDRESS 0x6440 0x6442 0x6446 SIZE (x16) 1 1 1 EALLOW PROTECTED Yes No Yes DESCRIPTION Comparator Control Register Comparator Status Register DAC Value Register Copyright © 2009­2010, Texas Instruments Incorporated Peripherals Submit Documentation Feedback Product Folder Link(s): TMS320F28030 TMS320F28031 TMS320F28032 TMS320F28033 TMS320F28034 TMS320F28035 55 TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584D ­ APRIL 2009 ­ REVISED JUNE 2010 www. ti. com 4. 3 Serial Peripheral Interface (SPI) Module The device includes the four-pin serial peripheral interface (SPI) module. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. 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