User manual TEXAS INSTRUMENTS TMS320F2806 DATA MANUAL REV L

[. . . ] TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 Digital Signal Processors Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Literature Number: SPRS230L October 2003 ­ Revised December 2009 TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L ­ OCTOBER 2003 ­ REVISED DECEMBER 2009 www. ti. com Contents 1 F280x, F2801x, C280x DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 3 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [. . . ] Watchdog Module The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode. The WDINT signal is fed to the LPM block so that it can wake the device from STANDBY (if enabled). In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of IDLE mode. In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so is the WATCHDOG. Copyright © 2003­2009, Texas Instruments Incorporated Functional Overview Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 51 TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L ­ OCTOBER 2003 ­ REVISED DECEMBER 2009 www. ti. com 3. 7 Low-Power Modes Block The low-power modes on the 280x are similar to the 240x devices. Low-Power Modes MODE IDLE STANDBY HALT (1) (2) (3) LPMCR0(1:0) 00 01 1X OSCCLK On On (watchdog still running) Off (oscillator and PLL turned off, watchdog not functional) CLKIN On Off Off SYSCLKOUT On (2) Off Off EXIT (1) XRS, Watchdog interrupt, any enabled interrupt, XNMI XRS, Watchdog interrupt, GPIO Port A signal, debugger (3), XNMI XRS, GPIO Port A signal, XNMI, debugger (3) The Exit column lists which signals or under what conditions the low power mode will be exited. A low signal, on any of the signals, will exit the low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise the IDLE mode will not be exited and the device will go back into the indicated low power mode. On the C28x, the clock output from the CPU (SYSCLKOUT) is still functional while on the 24x/240x the clock is turned off. On the C28x, the JTAG port can still function even if the CPU clock (CLKIN) is turned off. The various low-power modes operate as follows: IDLE Mode: This mode is exited by any enabled interrupt or an XNMI that is recognized by the processor. The LPM block performs no tasks during this mode as long as the LPMCR0(LPM) bits are set to 0, 0. Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY mode. The user must select which signal(s) will wake the device in the GPIOLPMSEL register. The selected signal(s) are also qualified by the OSCCLK before waking the device. Only the XRS and any GPIO port A signal (GPIO[31:0]) can wake the device from HALT mode. The user selects the signal in the GPIOLPMSEL register. STANDBY Mode: HALT Mode: NOTE The low-power modes do not affect the state of the output pins (PWM pins included). They will be in whatever state the code left them in when the IDLE instruction was executed. See the TMS320x280x, 2801x, 2804x DSP System Control and Interrupts Reference Guide (literature number SPRU712) for more details. 52 Functional Overview Copyright © 2003­2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 www. ti. com SPRS230L ­ OCTOBER 2003 ­ REVISED DECEMBER 2009 4 Peripherals The integrated peripherals of the 280x are described in the following subsections: · Three 32-bit CPU-Timers · Up to six enhanced PWM modules (ePWM1, ePWM2, ePWM3, ePWM4, ePWM5, ePWM6) · Up to four enhanced capture modules (eCAP1, eCAP2, eCAP3, eCAP4) · Up to two enhanced QEP modules (eQEP1, eQEP2) · Enhanced analog-to-digital converter (ADC) module · Up to two enhanced controller area network (eCAN) modules (eCAN-A, eCAN-B) · Up to two serial communications interface modules (SCI-A, SCI-B) · Up to four serial peripheral interface (SPI) modules (SPI-A, SPI-B, SPI-C, SPI-D) · Inter-integrated circuit module (I2C) · Digital I/O and shared pin functions 4. 1 32-Bit CPU-Timers 0/1/2 There are three 32-bit CPU-timers on the 280x devices (CPU-TIMER0/1/2). These timers are different from the timers that are present in the ePWM modules. NOTE If the application is not using DSP/BIOS, then CPU-Timer 2 can be used in the application. Reset Timer Reload 16-Bit Timer Divide-Down TDDRH:TDDR 32-Bit Timer Period PRDH:PRD SYSCLKOUT TCR. 4 (Timer Start Status) 16-Bit Prescale Counter PSCH:PSC Borrow 32-Bit Counter TIMH:TIM Borrow TINT Figure 4-1. CPU-Timers Copyright © 2003­2009, Texas Instruments Incorporated Peripherals Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 53 TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 SPRS230L ­ OCTOBER 2003 ­ REVISED DECEMBER 2009 www. ti. com In the 280x devices, the timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in Figure 4-2. INT1 to INT12 PIE TINT0 CPU-TIMER 0 C28x TINT1 INT13 XINT13 INT14 TINT2 CPU-TIMER 2 (Reserved for DSP/BIOS) CPU-TIMER 1 A. B. The timer registers are connected to the memory bus of the C28x processor. The timing of the timers is synchronized to SYSCLKOUT of the processor clock. Figure 4-2. [. . . ] Falls within JEDEC MS-026 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. [. . . ]