User manual TEXAS INSTRUMENTS TMS320F2812 DATA MANUAL REV R

[. . . ] TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812 Digital Signal Processors Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Literature Number: SPRS174R April 2001 ­ Revised May 2010 TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812 SPRS174R ­ APRIL 2001 ­ REVISED MAY 2010 www. ti. com Contents 1 2 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1. 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [. . . ] EVA and EVB timers, compare units, and capture units function identically. Table 4-2 shows the features and functionality available for the event-manager modules and highlights EVA nomenclature. Event managers A and B have identical peripheral register sets with EVA starting at 7400h and EVB starting at 7500h. The paragraphs in this section describe the function of GP timers, compare units, capture units, and QEPs using EVA nomenclature. These paragraphs are applicable to EVB with regard to function--however, module/signal names would differ. For more information, see the TMS320x281x DSP Event Manager (EV) Reference Guide (literature number SPRU065). Module and Signal Names for EVA and EVB EVENT MANAGER MODULES GP Timers Compare Units EVA MODULE GP Timer 1 GP Timer 2 Compare 1 Compare 2 Compare 3 Capture 1 Capture 2 Capture 3 QEP1 QEP2 QEPI1 Direction External Clock Compare SIGNAL T1PWM/T1CMP T2PWM/T2CMP PWM1/2 PWM3/4 PWM5/6 CAP1 CAP2 CAP3 QEP1 QEP2 TDIRA TCLKINA C1TRIP C2TRIP C3TRIP T1CTRIP_PDPINTA (1) T2CTRIP/EVASOC MODULE GP Timer 3 GP Timer 4 Compare 4 Compare 5 Compare 6 Capture 4 Capture 5 Capture 6 QEP3 QEP4 QEPI2 Direction External Clock Compare EVB SIGNAL T3PWM/T3CMP T4PWM/T4CMP PWM7/8 PWM9/10 PWM11/12 CAP4 CAP5 CAP6 QEP3 QEP4 TDIRB TCLKINB C4TRIP C5TRIP C6TRIP T3CTRIP_PDPINTB (1) T4CTRIP/EVBSOC Capture Units QEP Channels External Clock Inputs External Trip Inputs External Trip Inputs (1) In the 24x/240x-compatible mode, the T1CTRIP_PDPINTA pin functions as PDPINTA and the T3CTRIP_PDPINTB pin functions as PDPINTB. 58 Peripherals Copyright © 2001­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812 TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812 www. ti. com SPRS174R ­ APRIL 2001 ­ REVISED MAY 2010 Table 4-3. EVA Registers (1) NAME GPTCONA T1CNT T1CMPR T1PR T1CON T2CNT T2CMPR T2PR T2CON EXTCONA ACTRA DBTCONA CMPR1 CMPR2 CMPR3 CAPCONA CAPFIFOA CAP1FIFO CAP2FIFO CAP3FIFO CAP1FBOT CAP2FBOT CAP3FBOT EVAIMRA EVAIMRB EVAIMRC EVAIFRA EVAIFRB EVAIFRC (1) (2) (2) ADDRESS 0x00 7400 0x00 7401 0x00 7402 0x00 7403 0x00 7404 0x00 7405 0x00 7406 0x00 7407 0x00 7408 0x00 7409 0x00 7411 0x00 7413 0x00 7415 0x00 7417 0x00 7418 0x00 7419 0x00 7420 0x00 7422 0x00 7423 0x00 7424 0x00 7425 0x00 7427 0x00 7428 0x00 7429 0x00 742C 0x00 742D 0x00 742E 0x00 742F 0x00 7430 0x00 7431 SIZE (x16) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GP Timer Control Register A GP Timer 1 Counter Register GP Timer 1 Compare Register GP Timer 1 Period Register GP Timer 1 Control Register GP Timer 2 Counter Register GP Timer 2 Compare Register GP Timer 2 Period Register GP Timer 2 Control Register DESCRIPTION GP Extension Control Register A Compare Control Register A Compare Action Control Register A Dead-Band Timer Control Register A Compare Register 1 Compare Register 2 Compare Register 3 Capture Control Register A Capture FIFO Status Register A Two-Level-Deep Capture FIFO Stack 1 Two-Level-Deep Capture FIFO Stack 2 Two-Level-Deep Capture FIFO Stack 3 Bottom Register of Capture FIFO Stack 1 Bottom Register of Capture FIFO Stack 2 Bottom Register of Capture FIFO Stack 3 Interrupt Mask Register A Interrupt Mask Register B Interrupt Mask Register C Interrupt Flag Register A Interrupt Flag Register B Interrupt Flag Register C COMCONA The EV-B register set is identical except the address range is from 0x00 7500 to 0x00 753F. New register compared to 24x/240x Copyright © 2001­2010, Texas Instruments Incorporated Peripherals Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812 59 TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812 SPRS174R ­ APRIL 2001 ­ REVISED MAY 2010 www. ti. com GPTCONA[12:4], CAPCONA[8], EXTCONA[0] EVAENCLK EVATO ADC (Internal) Control Logic T1CTRIP/PDPINTA, T2CTRIP, C1TRIP, C2TRIP, C3TRIP EVASOC ADC (External) Timer 1 Compare T1CON[5, 4] Output Logic T1PWM_T1CMP 16 GPTCONA[1, 0] T1CON[1] clock GP Timer 1 dir T1CON[10:8] TDIRA Prescaler TCLKINA HSPCLK 16 T1CON[15:11, 6, 3, 2] PWM1 PWM2 PWM3 Dead-Band Logic Output Logic PWM4 PWM5 PWM6 Full Compare 1 Full Compare 2 SVPWM State Machine Peripheral Bus Full Compare 3 COMCONA[15:5, 2:0] ACTRA[15:12], COMCONA[12], T1CON[13:11] DBTCONA[15:0] ACTRA[11:0] Output Logic T2PWM_T2CMP Timer 2 Compare T2CON[5, 4] 16 T2CON[1] GPTCONA[3, 2] TCLKINA clock dir reset Prescaler QEPCLK T2CON[10:8] HSPCLK GP Timer 2 16 T2CON[15:11, 7, 6, 3, 2, 0] QEPDIR QEP Logic TDIRA CAPCONA[10, 9] 16 CAP1_QEP1 Capture Units Index Qual CAPCONA[15:12, 7:0] EXTCONA[1:2] CAP2_QEP2 CAP3_QEPI1 A. The EVB module is similar to the EVA module. Figure 4-3. Event Manager A Functional Block Diagram 60 Peripherals Copyright © 2001­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812 TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812 www. ti. com SPRS174R ­ APRIL 2001 ­ REVISED MAY 2010 4. 2. 1 General-Purpose (GP) Timers There are two GP timers. The GP timer x (x = 1 or 2 for EVA; x = 3 or 4 for EVB) includes: · A 16-bit timer, up-/down-counter, TxCNT, for reads or writes · A 16-bit timer-compare register, TxCMPR (double-buffered with shadow register), for reads or writes · A 16-bit timer-period register, TxPR (double-buffered with shadow register), for reads or writes · A 16-bit timer-control register, TxCON, for reads or writes · Selectable internal or external input clocks · A programmable prescaler for internal or external clock inputs · Control and interrupt logic, for four maskable interrupts: underflow, overflow, timer compare, and period interrupts · A selectable direction input pin (TDIRx) (to count up or down when directional up-/down-count mode is selected) The GP timers can be operated independently or synchronized with each other. The compare register associated with each GP timer can be used for compare function and PWM-waveform generation. There are three continuous modes of operations for each GP timer in up- or up/down-counting operations. Internal or external input clocks with programmable prescaler are used for each GP timer. GP timers also provide the time base for the other event-manager submodules: GP timer 1 for all the compares and PWM circuits, GP timer 2/1 for the capture units and the quadrature-pulse counting operations. Double-buffering of the period and compare registers allows programmable change of the timer (PWM) period and the compare/PWM pulse width as needed. 4. 2. 2 Full-Compare Units There are three full-compare units on each event manager. These compare units use GP timer1 as the time base and generate six outputs for compare and PWM-waveform generation using programmable deadband circuit. The compare registers of the compare units are double-buffered, allowing programmable change of the compare/PWM pulse widths as needed. 4. 2. 3 Programmable Deadband Generator Deadband generation can be enabled/disabled for each compare unit output individually. The deadband-generator circuit produces two outputs (with or without deadband zone) for each compare unit output signal. The output states of the deadband generator are configurable and changeable as needed by way of the double-buffered ACTRx register. 4. 2. 4 PWM Waveform Generation Up to eight PWM waveforms (outputs) can be generated simultaneously by each event manager: three independent pairs (six outputs) by the three full-compare units with programmable deadbands, and two independent PWMs by the GP-timer compares. 4. 2. 5 Double Update PWM Mode The F281x and C281x Event Manager supports "Double Update PWM Mode. " This mode refers to a PWM operation mode in which the position of the leading edge and the position of the trailing edge of a PWM pulse are independently modifiable in each PWM period. To support this mode, the compare register that determines the position of the edges of a PWM pulse must allow (buffered) compare value update once at the beginning of a PWM period and another time in the middle of a PWM period. The compare registers in F281x and C281x Event Managers are all buffered and support three compare value reload/update (value in buffer becoming active) modes. [. . . ] Falls within JEDEC MO-136 POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. [. . . ]